Decoupling capacitor on strain relaxation buffer layer
An electrical device including a substrate structure including a relaxed region of alternating layers of at least a first semiconductor material and a second semiconductor material. A first region of the substrate structure includes a first type conductivity semiconductor device having a first strain over a first portion of the relaxed region. A second region of the substrate structure includes a second type conductivity semiconductor device having a second strain over a second portion of the relaxed region. A third region of the substrate structure including a trench capacitor extending into relaxed region, wherein a width of the trench capacitor defined by the end to end distance of the node dielectric for the trench capacitor alternates between at least two width dimensions as a function of depth measured from the upper surface of the substrate structure.
1. A method of forming an electronic device comprising:
providing a substrate structure including a strain relaxed buffer region in a relaxed region;
forming a tensile strained semiconductor material layer on a first portion of the relaxed region;
forming a compressive strained semiconductor material layer on a second portion of the relaxed region;
forming a first semiconductor device on the tensile strained semiconductor material layer and a second semiconductor device on the compressive strained semiconductor material layer; and
forming a trench capacitor in a third portion of the relaxed region at a depth within the strain relaxed buffer region, wherein a width of the trench capacitor alternates between at least two width dimensions, the trench capacitor including a node dielectric on sidewalls of a trench containing said trench capacitor, wherein the node dielectric extends vertically along a sidewall of an interlevel dielectric to provide that an upper surface of the node dielectric is coplanar with an upper surface of gate structures for said first semiconductor device and said second semiconductor device.
2. The method of claim 1 , wherein the relaxed region is formed on a silicon (Si) substrate.
3. The method of claim 1 , wherein the relaxed region comprises a first semiconductor material of silicon and a second semiconductor material of silicon germanium comprising 25% germanium or less.
4. The method of claim 3 , wherein the first and second semiconductor material layer have a thickness of 45 nm or less.
5. The method of claim 1 , wherein the tensile strained semiconductor material layer is a silicon (Si) layer that is present on the second semiconductor material.
6. The method of claim 1 , wherein the compressive strained semiconductor material is a silicon and germanium containing layer that is present on the second semiconductor material layer.
7. The method of claim 6 , wherein the silicon and germanium containing layer comprises greater than 25% germanium.
8. The method of claim 1 , wherein said forming the trench capacitor in the third portion of the relaxed region comprises:
etching a trench into a portion of the relaxed region that is separate from the portions underlying the first and second semiconductor devices;
laterally etching one of the first semiconductor material and the second semiconductor material selectively to the other of the first semiconductor material and the second semiconductor material;
forming a first electrode on sidewalls of the first semiconductor material and the second semiconductor material that provide the trench;
depositing a node dielectric layer conformally on the sidewalls of the trench; and
filling at least a portion of the trench with a second electrode.
9. The method of claim 8 , wherein etching the trench comprises an anisotropic etch.
10. The method of claim 8 , wherein the lateral etch comprises H 2 O 2 wet chemical etching.
11. The method of claim 8 , wherein the first electrode is formed using gas phase doping.
12. The method of claim 8 , wherein the node dielectric is a high-k dielectric material.
13. The method of claim 12 , wherein the high-k dielectric material is deposited using atomic layer deposition.
14. The method of claim 8 , wherein the second electrode is a metal deposited using atomic layer deposition.
15. A method of forming an electronic device comprising:
providing a substrate structure including a strain relaxed buffer region in a relaxed region;
forming a first strained semiconductor on a first side of the relaxed region;
forming a second strained semiconductor on a second side of the relaxed region; and
forming a trench capacitor in a third portion of the relaxed region within the strain relaxed buffer region, wherein a width of the trench capacitor alternates between at least two width dimensions, a node dielectric of the capacitor being a conformal layer on an entirety of a sidewall of a trench containing said trench capacitor, wherein the node dielectric extends vertically along a sidewall of an interlevel dielectric to provide that an upper surface of the node dielectric is coplanar with an upper surface of gate structures for semiconductor devices present on the first strained semiconductor and the second strained semiconductor.
16. The method of claim 15 , wherein the relaxed region is formed on a silicon (Si) substrate.
17. The method of claim 16 , wherein the relaxed region comprises a first semiconductor material of silicon and a second semiconductor material of silicon germanium comprising 25% germanium or less.
18. The method of claim 17 , wherein the first and second semiconductor material layer have a thickness of 45 nm or less.
19. The method of claim 18 , wherein said forming the trench capacitor comprises:
etching a trench into a portion of the relaxed region;
laterally etching one of the first semiconductor material and the second semiconductor material selectively to the other of the first semiconductor material and the second semiconductor material;
forming a first electrode on sidewalls of the first semiconductor material and the second semiconductor material that provide the trench;
depositing a node dielectric layer conformally on the sidewalls of the trench; and
filling at least a portion of the trench with a second electrode.
20. The method of claim 19 , wherein etching the trench comprises an anisotropic etch.