Self-aligned low dielectric constant gate cap and a method of forming the same
According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate; a contact region self-aligned to the gate; and a low dielectric constant oxide having a dielectric constant of less than 3.9 located on top of the gate. According to an embodiment of the present invention, a method of forming a self-aligned contact comprises removing at least a portion of an interlayer dielectric layer to expose a top surface of a gate cap located on a substrate; recessing the gate cap to form a recessed area; depositing a low dielectric constant oxide having a dielectric constant of less than 3.9 in the recessed area; and polishing a surface of the low dielectric constant oxide to expose a contact area.
1. A semiconductor structure, comprising:
a gate located on a substrate;
a gate cap surrounding a side of the gate, the gate cap extending up from a top surface of the substrate;
a first liner layer formed directly on sides of the gate cap and around sides and a bottom of a silicide layer, a bottom surface of the first liner layer being formed directly on the substrate, wherein a width of the gate cap has an inverse taper to a width of the first liner layer, and wherein the first liner layer extends up from the top surface of the substrate above a top surface of both the gate and the gate cap;
a second liner layer formed directly on top of the silicide layer, the first liner layer being free of the second liner layer;
a contact region above the second liner layer; and
a low dielectric constant oxide having a dielectric constant of less than 3.9 located on top of the gate.
2. The semiconductor structure of claim 1 , wherein the low dielectric constant oxide is in direct contact with a top surface of the gate.
3. The semiconductor structure of claim 1 , wherein a layer of the gate cap is located between the low dielectric constant oxide and a top surface of the gate.
4. The semiconductor structure of claim 3 , wherein the layer of the gate cap has a thickness of 1 to 20 nanometers.
5. The semiconductor structure of claim 1 , wherein the gate cap is selected from the group consisting of an oxide, a nitride, an oxynitride, or a combination comprising at least two or more of the foregoing.
6. The semiconductor structure of claim 1 , wherein the low dielectric constant oxide has a dielectric constant of 2.8 to 3.5.
7. The semiconductor structure of claim 1 , wherein the low dielectric constant oxide comprises a porous silicon dioxide.
8. The semiconductor structure of claim 1 , wherein the substrate is selected from the group consisting of silicon, germanium, silicon germanium, silicon carbide, silicon germanium carbon, gallium, gallium arsenide, indium arsenide, indium phosphide, or a combination comprising at least two or more of the foregoing.
9. The semiconductor structure of claim 1 , wherein the low dielectric constant oxide comprises a doped silicon dioxide.
10. The semiconductor structure of claim 1 , wherein the gate cap is selected from the group consisting of an oxide, a nitride, an oxynitride, or a combination comprising at least two or more of the foregoing; and
wherein the gate comprises one or more layers each independently selected from the group consisting of silicon, aluminum, carbon, nitrogen, titanium, tantalum, tungsten, germanium, or a combination comprising at least two or more of the foregoing.
11. A semiconductor structure comprising:
a gate on a substrate;
a gate cap comprising a first portion on the substrate and a second portion on a top surface of the gate, the second portion comprising a thickness of about 1 to about 20 nanometers, the gate cap extending up from a top surface of the substrate, wherein the first portion and the second portion of the gate cap comprise a same material; and
a first liner layer formed directly on sides of the gate cap and around sides and a bottom of a silicide layer, a bottom surface of the first liner layer being formed directly on the substrate, wherein a width of the gate cap has an inverse taper to a width of the first liner layer, and wherein the first liner layer extends up from the top surface of the substrate above a top surface of both the gate and the gate cap;
a second liner layer formed directly on top of the silicide layer, the first liner layer being free of the second liner layer;
a low dielectric constant oxide comprising a dielectric constant of less than 3.9 on a surface of the gate cap.
12. The semiconductor structure of claim 11 , wherein the low dielectric constant oxide comprises a dielectric constant of 2.8 to 3.5.
13. The semiconductor structure of claim 11 , wherein the low dielectric constant oxide comprises a porous silicon dioxide.
14. The semiconductor structure of claim 11 , wherein the low dielectric constant oxide comprises a doped silicon dioxide.
15. The semiconductor structure of claim 11 , wherein the gate cap is selected from the group consisting of an oxide, a nitride, an oxynitride, or a combination comprising at least two or more of the foregoing.
16. The semiconductor structure of claim 11 , wherein the substrate is selected from the group consisting of silicon, germanium, silicon germanium, silicon carbide, silicon germanium carbon, gallium, gallium arsenide, indium arsenide, indium phosphide, or a combination comprising at least two or more of the foregoing.
17. The semiconductor structure of claim 11 , wherein the gate cap further comprises one or more layers, each layer selected from the group consisting of silicon, aluminum, carbon, nitrogen, titanium, tantalum, tungsten, germanium, or a combination comprising at least two or more of the foregoing.