FABRICATION OF A VERTICAL TRANSISTOR WITH SELF-ALIGNED BOTTOM SOURCE/DRAIN
A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, including forming a doped layer on a substrate, forming one or more vertical fins on the doped layer, forming a protective layer on the one or more vertical fins, wherein the protective layer has a thickness, and forming at least one isolation trench by removing at least a portion of the protective layer on the doped layer, wherein the isolation trench is laterally offset from at least one of the one or more vertical fins by the thickness of the protective layer.
1 . A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, comprising:
forming a gate dielectric layer on a vertical fin and a bottom spacer on a doped layer region, wherein the vertical fin and the doped layer region are between a pair of dielectric spacers;
forming a work function layer on the gate dielectric layer;
forming a gate metal fill on the work function layer;
removing a portion of the gate metal fill, work function layer, gate dielectric layer, and bottom spacer to form a contact gap that exposes a top surface of the doped layer region; and
forming a gap liner on the top surface of the doped layer region, sidewalls of the pair of dielectric spacers, and a sidewall of the gate metal fill.
2 . The method of claim 1 , further comprising removing at least a portion of the gap liner on the top surface of the doped layer region.
3 . The method of claim 2 , further comprising forming a sacrificial spacer in the contact gap on a remaining portion of the gap liner and on the surface of the doped layer region.
4 . The method of claim 3 , further comprising forming a recess between the top surface of the vertical fin and the gate metal fill, work function layer, and gate dielectric layer, and forming a top spacer in the recess.
5 . The method of claim 4 , further comprising forming a top source/drain on the vertical fin.
6 . The method of claim 5 , further comprising forming a dielectric cover layer on the top source/drain, top spacer, and sacrificial spacer.
7 . The method of claim 6 , further comprising removing a portion of the dielectric cover layer, and removing the sacrificial spacer to form a contact via.
8 . The method of claim 7 , further comprising forming a metal contact in the contact via.
9 . The method of claim 8 , wherein the gap liner electrically isolates the gate metal fill from the metal contact.
10 . A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, comprising:
forming a gate dielectric layer on a vertical fin and a bottom spacer on a doped layer region, wherein the vertical fin and the doped layer region are between a pair of dielectric spacers;
forming a work function layer on the gate dielectric layer;
forming a gate metal fill on the work function layer;
removing a portion of the gate metal fill, work function layer, gate dielectric layer, and bottom spacer to form a contact gap that exposes a top surface of the doped layer region;
forming a gap liner on the top surface of the doped layer region, sidewalls of the pair of dielectric spacers, and a sidewall of the gate metal fill by a conformal deposition; and
removing at least a portion of the gap liner on the top surface of the doped layer region.
11 . The method of claim 10 , further comprising forming a sacrificial spacer in the contact gap on a remaining portion of the gap liner and on the surface of the doped layer region.
12 . The method of claim 11 , wherein the sacrificial spacer is selected from the group consisting of silicon oxide (SiO) and carbon doped silicon oxide (SiCO).
13 . The method of claim 12 , wherein the gap liner is silicon nitride (SiN).
14 . The method of claim 13 , wherein the material of the bottom spacer is selected from the group consisting of a silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), and silicon borocarbonitride (SiBCN).
15 . A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, comprising:
forming a gate dielectric layer on a pair of vertical fins and a bottom spacer on a doped layer region, wherein the pair of vertical fins and the doped layer region are between a pair of dielectric spacers;
forming a work function layer on the gate dielectric layer;
forming a gate metal fill on the work function layer;
removing a portion of the gate metal fill, work function layer, gate dielectric layer, and bottom spacer to form a contact gap that exposes a top surface of the doped layer region; and
forming a gap liner on the top surface of the doped layer region, sidewalls of the pair of dielectric spacers, and a sidewall of the gate metal fill.
16 . The method of claim 15 , wherein the pair of vertical fins are separated by a distance in the range of about 10 nm to about 100 nm.
17 . The method of claim 15 , wherein the doped layer region is silicon germanium (SiGe) doped with boron to form a p-type FET.
18 . The method of claim 17 , further comprising forming a single top source/drain on the pair of vertical fins, wherein the top source/drain is silicon germanium (SiGe) doped with boron to form a p-type FET.
19 . The method of claim 18 , wherein the dielectric spacer is silicon nitride (SiN) or silicon oxynitride (SiON).
20 . The method of claim 18 , further comprising forming a dielectric cover layer on the top source/drain and sacrificial spacer, and removing a portion of the dielectric cover layer, and removing the sacrificial spacer to form a contact via.