Semiconductor device and method of forming the semiconductor device
A semiconductor device includes a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second VFET formed on the substrate and connected to the first VFET, and including a second fin and a second gate formed on the second fin, and a third VFET formed on the substrate and including a third fin, the first gate being formed on the third fin.
1. A semiconductor device comprising:
a first vertical field effect transistor (VFET) formed on a substrate, and comprising a first fin and a first gate formed on the first fin;
a second VFET formed on the substrate and connected to the first VFET, and comprising a second fin and a second gate formed on the second fin; and
a third VFET formed on the substrate and comprising a third fin, the first gate being formed on the third fin.
2. The semiconductor device of claim 1 , wherein the first and second gates are formed on the third fin.
3. The semiconductor device of claim 2 , further comprising:
a fourth VFET formed on the substrate and connected to the third VFET, and comprising the semiconductor fin as a fourth fin, the first and second gates being formed on the fourth fin.
4. The semiconductor device of claim 1 , wherein the second VFET is connected in parallel to the first VFET, and the fourth VFET is connected in series to the third VFET.
5. The semiconductor device of claim 3 , wherein the first and second VFETs comprise first and second p-type VFETs, respectively, and the third and fourth VFETs comprise first and second n-type VFETs, respectively, and the semiconductor device comprises a complementary metal oxide semiconductor (CMOS) NAND device.
6. The semiconductor device of claim 5 , wherein the first and second VFETs are formed on an p-type substrate, and the third and fourth VFETs are formed on a n-type substrate, and
wherein the device further comprises:
a V DD contact formed on the p-type substrate; and
a ground contact formed on the n-type substrate.
7. The semiconductor device of claim 3 , wherein the first and second VFETs comprise first and second n-type VFETs, respectively, and the third and fourth VFETs comprise first and second p-type VFETs, respectively, and the semiconductor device comprises a complementary metal oxide semiconductor (CMOS) NOR device.
8. The semiconductor device of claim 7 , wherein the first and second VFETs are formed on an n-type substrate, and the third and fourth VFETs are formed on a p-type substrate, and
wherein the device further comprises:
a V DD contact formed on the n-type substrate; and
a ground contact formed on the p-type substrate.
9. The semiconductor device of claim 3 , wherein the second p-type VFET is formed adjacent to the first p-type VFET in a first direction, and the second n-type VFET is formed adjacent to the first n-type VFET in the first direction, and
wherein the first n-type VFET is formed adjacent to the first p-type VFET in a second direction perpendicular to the first direction, and the second n-type VFET is formed adjacent to the second p-type VFET in the second direction.
10. The semiconductor device of claim 1 , wherein the first gate is formed on the third fin of the third VFET under the second gate.
11. The semiconductor device of claim 10 , wherein the third fin of the third VFET comprises an undoped region between the first and second gates, and the undoped region is gated by a fringing effect which couples the first and second gates.
12. The semiconductor device of claim 11 , wherein a distance between the first and second gates on the third fin is in a range from 1 nm to 4 nm.
13. The semiconductor device of claim 3 , wherein the first gate is formed on the fourth fin of the fourth VFET under the second gate.
14. The semiconductor device of claim 13 , wherein the fourth fin of the fourth VFET comprises an undoped region between the first and second gates, and the undoped region is gated by a fringing effect which couples the first and second gates.
15. The semiconductor device of claim 14 , wherein a distance between the first and second gates on the fourth fin is in a range from 1 nm to 4 nm.
16. The semiconductor device of claim 3 , wherein the first gate comprises a first width on the first fin and a second width on the third and fourth fins, the first width being greater than the second width, and
wherein the second gate comprises a first width on the second fin and a second width on the third and fourth fins, the first width of the second gate being greater than the second width of the second gate.
17. The semiconductor device of claim 3 , further comprising:
a device-bus interconnect formed between the first and second fins, and the third and fourth fins.
18. The semiconductor device of claim 17 , where the device-bus interconnect comprises an inversion layer.
19. A semiconductor device comprising:
a first vertical field effect transistor (VFET) formed on a substrate, and comprising a first fin and a first gate formed on the first fin;
a second VFET formed on the substrate and connected to the first VFET, and comprising a second fin and a second gate formed on the second fin; and
a third VFET formed on the substrate and comprising a third fin, the first and second gates being formed on the third fin, the third fin comprising an undoped region between the first and second gates, and the undoped region being gated by a fringing effect which couples the first and second gates.
20. A method of forming a semiconductor device, comprising:
forming a first vertical field effect transistor (VFET) on a substrate, and comprising a first fin and a first gate formed on the first fin;
forming a second VFET on the substrate and connected to the first VFET, and comprising a second fin and a second gate formed on the second fin; and
forming a third VFET on the substrate and comprising a third fin, the first gate being formed on the third fin.