PATTERNED GATE DIELECTRICS FOR III-V-BASED CMOS CIRCUITS
Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.
1 . A method for forming a plurality of semiconductor devices, comprising:
forming a first channel region on a first semiconductor material;
forming a trench from the first semiconductor material;
forming a second channel region by filling the trench with a second semiconductor material, wherein a sidewall of the first semiconductor material is in contact with the second semiconductor material; and
forming a gate one or more of the first channel region and the second channel region.
2 . The method of claim 1 , wherein the first semiconductor material is one of a group IV semiconductor and a III-V semiconductor and wherein the second semiconductor material is the other of the group IV semiconductor and the III-V semiconductor and wherein the first channel region is coplanar with the second channel region.
3 . The method of claim 1 , further comprising forming a channel nitrogen-containing layer on one or more of the first channel region and the second channel region before forming the gate.
4 . The method of claim 3 , wherein forming the channel nitrogen-containing layer comprises forming the channel nitrogen-containing layer on only one of the first channel region and the second channel region.
5 . The method of claim 3 , wherein forming the channel nitrogen-containing layer comprises forming the channel nitrogen-containing layer on both the first channel region and the second channel region.
6 . The method of claim 1 , wherein forming the nitrogen-containing layer comprises treating a surface of the gate to form a nitrogen-containing gate dielectric layer.
7 . The method of claim 6 , wherein forming the nitrogen-containing layer comprises one of performing an ammonia anneal and exposing the dielectric layer to a nitrogen plasma.
8 . The method of claim 1 , further including forming a gate dielectric, wherein forming the gate comprises forming a first gate dielectric layer and a first gate over only one of the first channel region and the second channel region, further comprising:
forming a second gate dielectric layer on the other of the first channel region and the second channel region, wherein the second gate dielectric layer is formed from a dielectric material different from the material of the first gate dielectric layer; and
forming a second gate on the second dielectric layer, wherein the second gate is formed from a gate material different from the material of the first gate.
9 . A method for forming a plurality of semiconductor devices, comprising:
forming a first channel region on a first semiconductor material;
forming a trench within the first semiconductor material;
forming a second channel region by filling the trench with a second semiconductor material different from the first semiconductor material, wherein a sidewall of the first semiconductor material is in contact with the second semiconductor material; and
forming a gate on a gate dielectric including a nitrogen-containing layer in one or more of the first channel region and the second channel region.
10 . The method of claim 9 , wherein the first semiconductor material is one of a group IV semiconductor and a III-V semiconductor and wherein the second semiconductor material is the other of the group IV semiconductor and the III-V semiconductor and wherein the first channel region is coplanar with the second channel region.
11 . The method of claim 9 , further comprising forming a channel nitrogen-containing layer on one or more of the first channel region and the second channel region before forming the gate dielectric layer.
12 . The method of claim 11 , wherein forming the channel nitrogen-containing layer comprises forming the channel nitrogen-containing layer on only one of the first channel region and the second channel region.
13 . The method of claim 11 , wherein forming the channel nitrogen-containing layer comprises forming the channel nitrogen-containing layer on both the first channel region and the second channel region.
14 . The method of claim 9 , wherein forming the nitrogen containing layer comprises treating a surface of the gate dielectric to form a nitrogen containing gate dielectric layer.
15 . The method of claim 14 , wherein forming the nitrogen-containing layer comprises one of performing an ammonia anneal and exposing the one or more regions to a nitrogen plasma.
16 . The method of claim 9 , further including forming a gate dielectric, wherein forming the gate on the gate dielectric comprises forming a first gate dielectric layer and a first gate over only one of the first channel region and the second channel region, further comprising:
forming a second gate dielectric layer on the other of the first channel region and the second channel region, wherein the second gate dielectric layer is formed from a dielectric material different from the material of the first gate dielectric layer; and
forming a second gate on the second dielectric layer, wherein the second gate is formed from a gate material different from the material of the first gate.
17 . A semiconductor device, comprising:
a first channel region formed from a first semiconductor material;
a second channel region formed by removing a portion of the first semiconductor material from the second semiconductor region to form a trench, and filling the trench with a second semiconductor material, wherein a sidewall of the first semiconductor material is in contact with the second semiconductor material; and
a gate formed over one or more of the first channel region and the second channel region.
18 . The semiconductor device of claim 17 , wherein the first semiconductor material is one of a group IV semiconductor and a III-V semiconductor and wherein the second semiconductor material is the other of the group IV semiconductor and the III-V semiconductor.
19 . The semiconductor device of claim 17 , further comprising a gate dielectric layer, wherein a nitrogen-containing layer is formed on the top surface of the gate dielectric layer.
20 . The semiconductor device of claim 17 , wherein the nitrogen-containing layer is formed on only the first channel region and the gate comprises a first gate over the second channel region, further comprising:
a first gate dielectric layer formed over the first channel region, under the first gate;
a second gate dielectric layer formed over the second channel region from a dielectric material different from the dielectric material of the first gate dielectric layer; and
a second gate formed on the second gate dielectric layer from a gate material different from the gate material of the first gate.