On-chip MIM capacitor
A method for forming an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices includes forming a first capacitor electrode between gate structures in a capacitor region while forming contacts to source and drain (S/D) regions in a CMOS region. Gate structures are cut in the CMOS region and the capacitor region by etching a trench across the gate structures and filling the trench with a dielectric material. The gate structures and the dielectric material in the trench in the capacitor region are removed to form a position for an insulator and a second electrode. The insulator is deposited in the position. Gate metal is deposited to form gate conductors in the CMOS region and the second electrode in the capacitor region.
1. A device having an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices, comprising:
a first capacitor electrode formed between gate structure regions in a capacitor region and formed from contact metal for contacts to source and drain (S/D) regions in a CMOS region;
an insulator formed in contact with the first electrode in the gate structure regions in the capacitor region; and
a second electrode formed in a plurality of loops in contact with the insulator within the gate structure regions in the capacitor region to form the on-chip capacitor.
2. The device as recited in claim 1 , wherein the CMOS region includes fin field effect transistors.
3. The device as recited in claim 1 , wherein the insulator includes a dielectric spacer and a gate dielectric layer, wherein the gate dielectric layer is employed with gate structures in the CMOS region.
4. The device as recited in claim 1 , wherein the first and second electrodes include different materials.
5. The device as recited in claim 1 , further including a gate cut trench structure including cuts in the gate structures in the CMOS region at longitudinal end portions and midspan.
6. The device as recited in claim 1 , wherein the insulator includes sidewall spacers for the gate structures in the CMOS region and the capacitor region.
7. The device as recited in claim 1 , wherein the device includes a system-on-chip (SOC).
8. The device as recited in claim 1 , wherein the loop structures connect to a common conductive region formed in a gate cut trench in the capacitor region.
9. A device having an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices, comprising:
a first capacitor electrode formed between gate structure regions in a capacitor region;
a gate cut trench structure formed in the capacitor region and filled with a conductive material;
an insulator formed in contact with the first electrode in the gate structure regions in the capacitor region; and
a second electrode formed in contact with the insulator spacer within the gate structure regions in the capacitor region to form the on-chip capacitor.
10. The device as recited in claim 9 , wherein the insulator includes a dielectric spacer and a gate dielectric layer, wherein the gate dielectric layer is employed with gate structures in a CMOS region.
11. The device as recited in claim 9 , wherein the first and second electrodes include different materials.
12. The device as recited in claim 9 , wherein the gate cut trench structure includes cuts in the gate structures in a CMOS region at longitudinal end portions and midspan.
13. The device as recited in claim 9 , wherein the insulator includes sidewall spacers for the gate structures in a CMOS region and the capacitor region.
14. The device as recited in claim 9 , wherein the device includes a system-on-chip (SOC).
15. The device as recited in claim 9 , wherein the second electrode includes a plurality of loop structures in the capacitor region.
16. The device as recited in claim 15 , wherein the loop structures connect to a common conductive region formed in a gate cut trench in the capacitor region.
17. A device having an on-chip capacitor with complementary metal oxide semiconductor (CMOS) devices, comprising:
a gate structure disposed in a capacitor region and in a CMOS region;
insulating spacers disposed on sides of the gate structure in the capacitor region and the CMOS region;
a first electrode disposed between the insulating spacer of the gate structure in the capacitor region; and
a second electrode in contact with the insulating spacers such that the insulating spacers are disposed between the first electrode and the second electrode.
18. The device as recited in claim 17 , further including a gate cut trench structure including cuts in a gate structure in the CMOS region at longitudinal end portions and midspan.
19. The device as recited in claim 17 , wherein the first electrode forms a plurality of loops in the capacitor region.
20. The device as recited in claim 17 , wherein the insulating spacers include a dielectric spacer and a gate dielectric layer, wherein the gate dielectric layer is employed with gate structures in the CMOS region.