High-density metal-insulator-metal capacitor integration wth nanosheet stack technology
An approach provides a metal-insulator-metal capacitor with a comb-like structure. The metal-insulator-metal capacitor includes a first electrode material forming a central, vertical portion of the first electrode metal and two sets of stacked horizontal portions of the first electrode metal. An insulator material surrounds the first electrode metal and exposes a top surface of the central, vertical portion of the first electrode metal. The metal-insulator-metal capacitor includes a second electrode material surrounding the insulator material. The metal-insulator-metal capacitor includes a first electrode contact connecting to the top surface of the central, vertical portion of the first electrode metal and a second electrode contact connecting to a top surface of the second electrode material.
1 . A metal-insulator-metal capacitor, the metal-insulator-metal capacitor comprising:
a first electrode metal forming a central, vertical portion of the first electrode metal and two sets of stacked horizontal portions of the first electrode metal, wherein the central, vertical portion of the first electrode metal extends above a topmost horizontal portion of the two sets of stacked horizontal portions of the first electrode metal;
an insulator material surrounding the first electrode metal and exposing a top surface of the central, vertical portion of the first electrode metal;
a second electrode material surrounding the insulator material, wherein the insulator material comprises a same material as a gate dielectric material covering bottom and sidewall surfaces of the second electrode material;
a first electrode contact connecting to the top surface of the central, vertical portion of the first electrode metal; and
a second electrode contact connecting to a top surface of the second electrode material.
2 . The metal-insulator-metal capacitor of claim 1 , wherein the second electrode material is a gate electrode material forming a rectangular shape around the first electrode metal.
3 . The metal-insulator-metal capacitor of claim 1 , wherein the two sets of stacked horizontal portions of the first electrode metal extend on either side of the central, vertical portion of the first electrode metal.
4 . The metal-insulator-metal capacitor of claim 1 , wherein the insulator material surrounding the first electrode metal is a multilayer dielectric material.
5 . The metal-insulator-metal capacitor of claim 1 , wherein the insulator material surrounding the first electrode metal is a same material as a high-k dielectric material in one or more logic devices on a same semiconductor substrate.
6 . The metal-insulator-metal capacitor of claim 1 , wherein the gate dielectric material covering the sidewall surfaces of the second electrode material is located between a portion of a sidewall spacer and the second electrode material.
7 . The metal-insulator-metal capacitor of claim 1 , wherein the second electrode contact connecting to the top surface of the second electrode material connects to the top surface of the second electrode material above one of the two sets of stacked horizontal portions of the first electrode metal.
8 . The metal-insulator-metal capacitor of claim 1 , wherein the second electrode material encases the insulator material that is over the two sets of stacked horizontal portions of the first electrode metal.
9 . The metal-insulator-metal capacitor of claim 1 , wherein the two sets of stacked horizontal portions of the first electrode metal have outer edges that are each separated by an inner spacer.
10 . The metal-insulator-metal capacitor of claim 1 , wherein the two sets of stacked horizontal portions of the first electrode metal inside the insulator material form a comb-like metal-insulator-metal capacitor structure.
11 . A metal-insulator-metal capacitor, the metal-insulator-metal capacitor comprising:
a first electrode metal forming multiple central, vertical portions of the first electrode metal and multiple sets of stacked horizontal portions of the first electrode metal, wherein the multiple central, vertical portions of the first electrode metal extend above a topmost horizontal portion of the multiple sets of stacked horizontal portions of the first electrode metal;
an insulator material surrounding the first electrode metal and exposing a top surface of each of the central, vertical portions of the first electrode metal;
a second electrode material surrounding the insulator material, wherein the insulator material comprises a same material as a gate dielectric material covering bottom and sidewall surfaces of the second electrode material;
a first electrode contact connecting to each of the top surface of the multiple central, vertical portions of the first electrode metal; and
a second electrode contact connecting to a top surface of the second electrode material on either side of each of the multiple central, vertical portions of the first electrode metal.
12 . The metal-insulator-metal capacitor of claim 11 , wherein the second electrode material covers a center portion of each of the multiple sets of stacked horizontal portions of the first electrode metal.
13 . The metal-insulator-metal capacitor of claim 12 , wherein each of the multiple sets of stacked horizontal portions of the first electrode metal include an inner spacer between outer edges of each layer of the first electrode metal in the multiple sets of stacked horizontal portions of the first electrode metal.
14 . The metal-insulator-metal capacitor of claim 11 , wherein the insulator surrounding the first electrode metal is formed simultaneously with a gate dielectric material in one or more logic devices in a different region of a same semiconductor substrate.
15 . A method of forming a metal-insulator-metal capacitor with a comb-like structure, the method comprising:
forming, from a first electrode metal, a central, vertical portion of the first electrode metal and two sets of stacked horizontal portions of the first electrode metal, wherein the central, vertical portion of the first electrode metal extends above a topmost horizontal portion of the two sets of stacked horizontal portions of the first electrode metal;
depositing an insulator material, the insulator material surrounding the first electrode material and exposing a top surface of the central, vertical portion of the first electrode metal;
depositing a second electrode material, the second electrode material surrounding the insulator material, wherein the insulator material comprises a same material as a gate dielectric material covering bottom and sidewall surfaces of the second electrode material;
forming a first electrode contact on a top surface of the central, vertical portion of the first electrode metal; and
forming a second electrode contact to a top surface of the second electrode.
16 . The method of claim 15 , further comprising forming a sidewall spacer on vertical sides of the gate dielectric material.
17 . The method of claim 16 , wherein the insulator material surrounding the first electrode is formed simultaneously with the gate dielectric material in one or more logic devices of a same semiconductor substrate.
18 . The method of claim 15 , wherein the insulator material surrounding the first electrode metal comprises a multilayer dielectric material.
19 . The method of claim 18 , wherein the multilayer dielectric material includes at least one layer of a high-k dielectric material.