Metal insulator metal capacitor (MIM capacitor)
A semiconductor device including a metal insulator metal capacitor (MIM capacitor), a first via connected to and through a bottom plate of the MIM, and a middle plate of the MIM, where a middle isolated portion of the middle plate of the MIM surrounds the first via. A MIM capacitor, a first via connected to and through a bottom plate of the MIM, and a middle plate of the MIM, where a middle isolated portion of the middle plate of the MIM surrounds the first via, where the middle isolated portion is surrounded by a middle isolation dielectric on all vertical side surfaces. Forming a MIM capacitor, forming a first via connected to and through a bottom plate of the MIM, and forming a middle plate of the MIM, where a middle isolated portion of the middle plate of the MIM surrounds the first via.
1 . A semiconductor device comprising:
a metal insulator metal capacitor (MIM capacitor) within back end of line circuitry of the semiconductor device;
a first via connected to and through a bottom plate of the MIM;
an outer plate of the MIM, wherein an outer electrode of the MIM comprises the bottom plate and a top plate, wherein an entirety of each of an upper horizontal surface of the bottom plate and an upper horizontal surface of the top plate lies in a single plane and an entirety of each of a lower horizontal surface of the bottom plate and a lower horizontal surface of the top plate lies in a single plane; and
a middle plate of the MIM, wherein an inner electrode of the MIM comprises the middle plate, wherein an entirety of each of an upper horizontal surface and a lower horizontal surface of the middle plate lies in a single plane, wherein
a middle isolated portion of the middle plate of the MIM surrounds the first via.
2 . The semiconductor device according to claim 1 , wherein
the middle isolated portion is surrounded by a middle isolation dielectric on all vertical side surfaces.
3 . The semiconductor device according to claim 2 , wherein
the middle isolation dielectric comprises an outline of a rectangular shape from a top view.
4 . The semiconductor device according to claim 1 , wherein
the bottom plate is horizontally below the middle plate, and
the top plate is horizontally above the middle plate.
5 . The semiconductor device according to claim 4 , further comprising:
a second via connected to and through the middle plate of the MIM, wherein
a bottom isolated portion of the bottom plate surrounds the second via, wherein
the bottom isolated portion is surrounded by a bottom isolation dielectric on all vertical side surfaces.
6 . The semiconductor device according to claim 5 , wherein
the second via is connected to and through the middle plate, and is connected to and through the bottom isolated portion.
7 . The semiconductor device according to claim 6 , wherein
the second via is connected to and through a top isolated portion of the top plate.
8 . The semiconductor device according to claim 6 , wherein
the bottom plate comprises a single planar upper horizontal surface and a single planar lower horizontal surface;
the middle plate comprises a single planar upper horizontal surface and a single planar lower horizontal surface.
9 . A semiconductor device comprising:
a metal insulator metal capacitor (MIM capacitor) within back end of line circuitry of the semiconductor device;
a first via connected to and through a bottom plate of the MIM;
an outer plate of the MIM, wherein an outer electrode of the MIM comprises the bottom plate and a top plate, wherein the bottom plate is comprised of titanium nitride (TiN), wherein an entirety of each of an upper horizontal surface of the bottom plate and an upper horizontal surface of the top plate lies in a single plane and an entirety of each of a lower horizontal surface of the bottom plate and a lower horizontal surface of the top plate lies in a single plane; and
a middle plate of the MIM, wherein an inner electrode of the MIM comprises the middle plate, wherein an entirety of each of an upper horizontal surface and a lower horizontal surface of the middle plate lies in a single plane, wherein
a middle isolated portion of the middle plate of the MIM surrounds the first via, wherein
the middle isolated portion is surrounded by a middle isolation dielectric on all vertical side surfaces.
10 . The semiconductor device according to claim 9 , wherein
the middle isolation dielectric comprises an outline of a rectangular shape from a top view.
11 . The semiconductor device according to claim 10 , wherein
the bottom plate is horizontally below the middle plate, and
the top plate is horizontally above the middle plate.
12 . The semiconductor device according to claim 11 , further comprising:
a second via connected to and through the middle plate of the MIM, wherein
a bottom isolated portion of the bottom plate surrounds the second via, wherein
the bottom isolated portion is surrounded by a bottom isolation dielectric on all vertical sides.
13 . The semiconductor device according to claim 12 , wherein
the first via is connected to and through the middle plate, and is connected to and through the middle isolated portion.
14 . The semiconductor device according to claim 13 , further comprising:
the second via is connected to and through the bottom isolated portion, and is connected to and through a top isolated portion of the top plate.
15 . The semiconductor device according to claim 14 , wherein
the bottom plate comprises a single planar upper horizontal surface and a single planar lower horizontal surface;
the middle plate comprises a single planar upper horizontal surface and a single planar lower horizontal surface.
16 . A method of forming a semiconductor device comprising:
forming a metal insulator metal capacitor (MIM capacitor) within back end of line circuitry of the semiconductor device;
forming a first via connected to and through a bottom plate of the MIM;
forming an outer plate of the MIM, wherein an outer electrode of the MIM comprises the bottom plate and a top plate, wherein an entirety of each of an upper horizontal surface of the bottom plate and an upper horizontal surface of the top plate lies in a single plane and an entirety of each of a lower horizontal surface of the bottom plate and a lower horizontal surface of the top plate lies in a single plane; and
forming a middle plate of the MIM, wherein an inner electrode of the MIM comprises the middle plate, wherein an entirety of each of an upper horizontal surface and a lower horizontal surface of the middle plate lies in a single plane, wherein
a middle isolated portion of the middle plate of the MIM surrounds the first via.
17 . The method according to claim 16 , wherein
the middle isolated portion is surrounded by a middle isolation dielectric on all vertical side surfaces.
18 . The method according to claim 17 , wherein
the middle isolation dielectric comprises an outline of a rectangular shape from a top view.
19 . The method according to claim 18 , wherein
the bottom plate is horizontally below the middle plate, and
the top plate is horizontally above the middle plate.
20 . The method according to claim 19 , further comprising:
forming a second via connected to and through the middle plate of the MIM, wherein
a bottom isolated portion of the bottom plate surrounds the second via, wherein
the bottom isolated portion is surrounded by a bottom isolation dielectric on all vertical sides, wherein
the bottom plate comprises a single planar upper horizontal surface and a single planar lower horizontal surface;
the middle plate comprises a single planar upper horizontal surface and a single planar lower horizontal surface.