Metal-insulator-metal capacitive structure and methods of fabricating thereof

1. A method comprising:

providing a top metal layer and an inter-metal dielectric (IMD);

forming a first silicon oxide layer adjacent a bottom electrode, wherein the forming the first silicon oxide layer includes: forming an opening in a conductive material to provide the bottom electrode, wherein the forming the opening includes etching the conductive material and a portion of the IMD, and chemical vapor deposition of silicon oxide into the opening;

depositing a first high-k dielectric layer over the bottom electrode and the first silicon oxide layer;

forming a middle electrode over the first high-k dielectric layer;

forming a second silicon oxide layer adjacent the middle electrode;

depositing a second high-k dielectric layer over the middle electrode and the second silicon oxide layer; and

forming a top electrode over the second high-k dielectric layer.

2. The method of claim 1 , further comprising:

forming an insulator layer over the top metal layer and the IMD; and wherein the bottom electrode is formed over the insulator layer.

3. The method of claim 1 , wherein the forming the first silicon oxide layer includes:

depositing a silicon oxide material; and

performing a chemical mechanical planarization (CMP) process.

4. The method of claim 3 , wherein the CMP process provides a planar surface comprising the silicon oxide material and the bottom electrode.

5. The method of claim 4 , wherein the depositing the first high-k dielectric layer over the bottom electrode and the first silicon oxide layer includes depositing the first high-k dielectric layer directly on the planar surface.

6. The method of claim 1 , wherein the forming the middle electrode over the first high-k dielectric layer includes:

depositing a conductive material as a conformal layer;

patterning the conformal layer to form an opening in the conductive material;

depositing the second silicon oxide layer in the opening; and

performing a chemical mechanical planarization (CMP) process on the second silicon oxide layer and the conductive material.

7. The method of claim 6 , wherein the performing the CMP process forms a planar surface of the second silicon oxide layer and the conductive material; and wherein the depositing the second high-k dielectric layer forms the second high-k dielectric layer directly on the planar surface.

8. The method of claim 1 , wherein the forming the first silicon oxide layer includes forming a substantially planar surface of

silicon oxide in the opening and the bottom electrode.

9. A method of fabricating a metal-insulator-metal (MIM) capacitor, the method comprising:

forming a first conductive material layer over a substrate;

patterning the first conductive material layer to form a first electrode and an opening;

depositing an oxide material in the opening;

performing a chemical mechanical polishing (CMP) process on the first electrode and deposited oxide material to form a planar surface, wherein after the CMP process the oxide material has a second thickness and the first electrode has a first thickness, the second thickness greater than the first thickness;

depositing a high-k dielectric material having a different composition than the oxide material on the planar surface; and

forming a second electrode over the high-k dielectric material.

10. The method of claim 9 , wherein the first conductive material layer is titanium nitride.

11. The method of claim 9 , wherein the planar surface includes a first portion defined by the first electrode and a second portion defined by the deposited oxide material.

12. The method of claim 11 , wherein the high-k dielectric material is deposited directly on the first portion and the second portion.

13. The method of claim 9 , wherein the deposited oxide material is approximately twice a thickness of the first electrode.

14. The method of claim 9 , wherein the forming the second electrode includes depositing a second conductive material layer and patterning the second conductive material layer to form the second electrode and another opening.

15. The method of claim 14 , further comprising:

filling the another opening with another oxide material; and

planarizing the another oxide material.

16. The method of claim 15 , further comprising:

forming a third electrode over the another oxide material.

17. A method of fabricating a metal-insulator-metal (MIM) capacitor structure, comprising:

providing a first silicon oxide layer adjacent and coplanar a bottom electrode formed over a substrate, wherein a bottom surface of the first silicon oxide layer is closer to the substrate than a bottom surface of the bottom electrode;

depositing a first high-k dielectric layer on the first silicon oxide layer and the bottom electrode;

forming a middle electrode over the first high-k dielectric layer;

forming a second oxide layer adjacent to and coplanar with the middle electrode;

depositing a second high-k dielectric layer over the second oxide layer and the middle electrode; and

forming a top electrode over the second high-k dielectric layer.

18. The method of claim 17 , wherein the first silicon oxide layer has a top surface substantially coplanar with a top surface of the bottom electrode.

19. The method of claim 17 , wherein the depositing the first high-k dielectric layer deposits material of the first high-k dielectric layer directly on the top surface of the first silicon oxide layer and the top surface of the bottom electrode.

20. The method of claim 17 , further comprising:

forming a top metal layer of a multi-layer interconnect prior to forming the bottom electrode.