FINFET WITH REDUCED PARASITIC CAPACITANCE
A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.
1 . A method of fabricating a semiconductor device, the method comprising:
patterning a blanket metal layer to form a source-drain contact on an upper surface of a self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from semiconductor fins to the source-drain contact, wherein the upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region; and
recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.
2 . The method of claim 1 , wherein recessing the portion of the self-aligned silicide contact comprises:
recessing all of the self-aligned silicide contact except for a portion directly beneath the source-drain contact.
3 . The method of claim 1 , wherein recessing the portion of the self-aligned silicide contact comprises:
recessing the self-aligned silicide contact to a maximum depth without exposing an upper surface of the semiconductor fins.
4 . The method of claim 1 , wherein recessing the portion of the self-aligned silicide contact comprises:
recessing the self-aligned silicide contact immediately after patterning the source-drain contact using the same etch chemistries used to pattern the blanket metal layer.
5 . The method of claim 1 , wherein the self-aligned silicide contact has a stepped profile after being recessed, the stepped profile comprising at least a first upper surface and a second upper surface, the first upper surface being in direct contact with the source-drain contact and above the second upper surface.
6 . The method of claim 5 , wherein a contact area between the source-drain contact and the self-aligned silicide contact is equal to a surface area of the first upper surface of the self-aligned silicide contact.
7 . The method of claim 5 , wherein vertical sidewalls of the self-aligned silicide contact between the first upper surface and the second upper surface are substantially flush with vertical sidewalls of the source-drain contact.
8 . The method of claim 1 , further comprising:
forming a gate contact from the blanket metal layer at the same time as forming the source-drain contact.
9 . The method of claim 1 , further comprising:
forming a gate contact after recessing the portion of the self-aligned silicide contact, the gate contact is in direct contact with a gate electrode.
10 . A method of fabricating a finFET semiconductor device, the method comprising:
forming a dummy gate above and perpendicular to semiconductor fins;
forming sidewall spacers on opposite sides of the dummy gate;
replacing the dummy gate with a metal gate electrode;
forming a self-aligned silicide contact on exposed portions of the semiconductor fins and adjacent to an isolation region, an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of the isolation region;
forming a blanket metal layer on top of both the metal gate electrode and the self-aligned silicide contact, the blanket metal layer being in direct contact with the self-aligned silicide contact but physically isolated from the metal gate electrode by a dielectric gate cap;
using a mask to pattern the blanket metal layer and form a source-drain contact; and
recessing a portion of the self-aligned silicide contact not covered by the source-drain contact using the mask.
11 . The method of claim 10 , wherein recessing the portion of the self-aligned silicide contact comprises:
recessing all of the self-aligned silicide contact except for a portion directly beneath the source-drain contact.
12 . The method of claim 10 , wherein the self-aligned silicide contact has a stepped profile after being recessed, the stepped profile comprising at least a first upper surface and a second upper surface, the first upper surface being in direct contact with the source-drain contact and above the second upper surface.
13 . The method of claim 12 , wherein a contact area between the source-drain contact and the self-aligned silicide contact is equal to a surface area of the first upper surface of the self-aligned silicide contact.
14 . The method of claim 12 , wherein vertical sidewalls of the self-aligned silicide contact between the first upper surface and the second upper surface are substantially flush with vertical sidewalls of the source-drain contact.