GATE PLANARITY FOR FINFET USING DUMMY POLISH STOP
A method for forming a semiconductor device includes depositing a dielectric layer over fins formed in a semiconductor substrate. The dielectric layer includes a screen layer over tops of the fins. An etch stop feature is formed on the screen layer. The etch stop feature is patterned down to the screen layer in regions across the device. A dummy gate material formed over the fins is planarized down to the etch stop feature, a dielectric fill between gate structures patterned from the dummy gate material is planarized down to the etch stop feature and a gate conductor is planarized to the etch stop feature.
1 . A method for forming a semiconductor device, comprising:
patterning an etch stop feature down to a screen layer in at least one etch stop region on the device; and
planarizing material in at least one active region of the device down to the etch stop feature, wherein the at least one active region includes a plurality of fins and is adjacent to the at least one etch stop region.
2 . The method as recited in claim 1 , wherein the etch stop feature includes multiple layers including different materials.
3 . The method as recited in claim 1 , wherein the etch stop feature includes a base layer formed from polysilicon or amorphous silicon and an etch stop layer formed on the base layer.
4 . The method as recited in claim 3 , further comprising forming electrical components from the base layer.
5 . The method as recited in claim 1 , wherein the etch stop layer includes a nitride material.
6 . The method as recited in claim 1 , wherein the etch stop feature includes a height configured to preserve a minimum gate height after gate formation processing.
7 . The method as recited in claim 1 , wherein the at least one etch stop region includes regions on the device where gates are not active.
8 . The method as recited in claim 1 , further comprising recessing a dielectric layer to expose the fins wherein the dielectric layer forms a shallow trench isolation structure.
9 . The method as recited in claim 1 , wherein the at least one active region comprises regions on the device where gates are active.
10 . The method as recited in claim 1 , further comprising forming the fins in the screen layer.
11 . A method for forming a semiconductor device, comprising:
depositing a dielectric layer over fins formed in a semiconductor substrate, the dielectric layer including a screen layer over tops of the fins;
forming a base layer on the screen layer and an etch stop layer on the base layer;
patterning the etch stop layer and the base layer down to the screen layer in a plurality of regions across the device to form an etch stop feature in each of the plurality of regions;
recessing the dielectric layer to expose the fins;
depositing a conformal screen dielectric over the fins and the etch stop layer;
forming gate structures and a dielectric fill over the fins by a replacement gate process; and
planarizing the gate structures and the dielectric fill down to the etch stop layer.
12 . The method as recited in claim 11 , wherein the base layer includes polysilicon or amorphous silicon.
13 . The method as recited in claim 11 , wherein the etch stop layer includes a nitride material.
14 . The method as recited in claim 11 , further comprising forming electrical components from the base layer.
15 . The method as recited in claim 11 , wherein the etch stop feature includes a height configured to preserve a minimum gate height after gate formation processing.
16 . The method as recited in claim 11 , wherein the plurality of regions includes regions on the device where gates are not active.
17 . The method as recited in claim 11 , further comprising recessing the dielectric layer to expose the fins wherein the dielectric layer forms a shallow trench isolation structure.
18 . The method as recited in claim 11 , wherein the base layer is formed from polysilicon or amorphous silicon.
19 . The method as recited in claim 11 , wherein the conformal screen dielectric protects the fins from subsequent processing.
20 . The method as recited in claim 11 , wherein the replacement gate process includes:
forming a dummy gate layer over the fins;
planarizing the dummy gate layer down to the etch stop layer;
forming a blanket dielectric and a hardmask over the dummy gate layer and the etch stop layer;
etching trenches into the hardmask, the blanket dielectic and the dummy gate layer down to the screen dielectric;
filling the trenches with a flowable dielectric;
etching the dummy date layer down to the screen dielectric to form gate openings; and
filling the gate openings with a gate conductor to form the gate structure.