Wimpy device by selective laser annealing
A device having co-integrated wimpy and nominal transistors includes first source/drain regions formed with a semiconductor alloy imparting strain into a first channel region. The device also has wimpy transistors including second source/drain regions formed with the semiconductor alloy that has been decomposed to include a larger amount of an electrically active atomic element than contained in the semiconductor alloy of the first source/drain region.
1. A device having co-integrated wimpy and nominal transistors, comprising:
nominal transistors including first source/drain regions formed with a semiconductor alloy imparting strain into a first channel region; and
wimpy transistors including second source/drain regions formed with the semiconductor alloy that has been decomposed to include a larger amount of an electrically active atomic element than contained in the semiconductor alloy of the first source/drain region, wherein the wimpy device structures have a same gate length, a same channel dopant, and a same contact pitch as the nominal device structures.
2. The device as recited in claim 1 , wherein each of the first source/drain regions and the second source/drain regions include silicon phosphide (Si 3 P 4 ).
3. The device as recited in claim 1 , wherein the second source/drain regions include more electrically active phosphorous than the first source/drain regions due to selective laser annealing.
4. The device as recited in claim 1 , wherein the first source/drain regions and the second source/drain regions have substantially the same resistance.
5. The device as recited in claim 1 , wherein the first source/drain regions and the second source/drain regions are formed on a dielectric layer.
6. The device as recited in claim 1 , wherein the first source/drain regions and the second source/drain regions are formed on fins etched from a semiconductor material.
7. The device as recited in claim 1 , wherein the first source/drain regions transfer about half of a stress introduced by the semiconductor alloy into channel regions.
8. The device as recited in claim 1 , wherein the first channel region is in a first gate structure including a first gate conductor and first spacer layers; and further comprising,
a second channel region in a second gate structure including a second gate conductor and second spacer layers.
9. The device as recited in claim 8 , wherein the first source/drain regions are adjacent to the first spacer layers; and
the second source/drain regions are adjacent to the second spacer layers.
10. The device as recited in claim 1 , wherein the first source/drain regions have a stress of about 1.6 GPa due to the semiconductor alloy.
11. A device having co-integrated wimpy and nominal transistors, comprising:
first fins and second fins formed on a substrate;
first source/drain regions formed on the first fins adjacent to a first gate structure to form nominal device structures with a first material; and
second source/drain regions formed on the second fins adjacent to a second gate structure to form wimpy device structures with a second material formed of decomposed first material;
wherein the wimpy device structures have a different concentration of an electrically conductive atomic element than the nominal device structures such that the wimpy device structures have different threshold voltages than the nominal device structures.
12. The device as recited in claim 11 , wherein the first material includes a Si 3 P 4 material.
13. The device as recited in claim 11 , wherein the wimpy device structures have a same gate length, same channel doping and same contact pitch as the nominal device structures.
14. The device as recited in claim 11 , wherein the first source/drain regions include strained material and the second source/drain regions include relaxed material due to laser selective annealing.
15. The device as recited in claim 11 , wherein the second source/drain regions include more electrically active phosphorous than the first source/drain regions due to selective laser annealing.
16. The device as recited in claim 11 , wherein the first source/drain regions and the second source/drain regions have substantially the same resistance.
17. The device as recited in claim 11 , wherein the first source/drain regions and the second source/drain regions are formed on a dielectric layer.
18. The device as recited in claim 11 , wherein the first source/drain regions transfer about half of stress introduced by the first material into channel regions.
19. The device as recited in claim 11 , wherein the first gate structure includes a first gate conductor and first spacer layers; and
the second gate structure includes a second gate conductor and second spacer layers.