Wimpy device by selective laser annealing
A method for co-integrating wimpy and nominal devices includes growing source/drain regions on semiconductor material adjacent to a gate structure to form device structures with a non-electrically active material. Selected device structures are masked with a block mask. Unmasked device structures are selectively annealed to increase electrical activity of the non-electrically active material to adjust a threshold voltage between the selected device structures and the unmasked device structures.
1. A device having co-integrated wimpy and nominal transistors, comprising:
nominal transistors including first source/drain regions formed with a semiconductor alloy imparting strain into a first channel region; and
wimpy transistors including second source/drain regions formed with the semiconductor alloy that has been decomposed to include a larger amount of an electrically active atomic element than contained in the semiconductor alloy of the first source/drain region and to relax the strain in a second channel region.
2. The device as recited in claim 1 , wherein the wimpy device structures have a same gate length, same channel doping and same contact pitch as the nominal device structures.
3. The device as recited in claim 1 , wherein each of the first source/drain regions and the second source/drain regions include silicon phosphide (Si 3 P 4 ).
4. The device as recited in claim 1 , wherein the second source/drain regions include more electrically active phosphorous than the first source/drain regions due to selective laser annealing.
5. The device as recited in claim 1 , wherein the first source/drain regions and the second source/drain regions have substantially the same resistance.
6. The device as recited in claim 1 , wherein the first source/drain regions and the second source/drain regions are formed on a dielectric layer.
7. The device as recited in claim 1 , wherein the first source/drain regions and the second source/drain regions are formed on fins etched from a semiconductor material.
8. The device as recited in claim 1 , wherein the first source/drain regions transfer about half of a stress introduced by the semiconductor alloy into channel regions.
9. The device as recited in claim 1 , wherein the first channel region is formed in a first gate structure including a first gate conductor and first spacer layers; and
the second channel region is formed in a second gate structure including a second gate conductor and second spacer layers.
10. The device as recited in claim 9 , wherein the first source/drain regions are adjacent to the first spacer layers; and
the second source/drain regions are adjacent to the second spacer layers.
11. The device as recited in claim 1 , wherein the first source/drain regions have a stress of about 1.6 GPa due to the semiconductor alloy.
12. A device having co-integrated wimpy and nominal transistors, comprising:
first fins and second fins formed on a substrate;
first source/drain regions formed on the first fins adjacent to a first gate structure to form nominal device structures with a first material; and
second source/drain regions formed on the second fins adjacent to a second gate structure to form wimpy device structures with a second material formed of decomposed first material;
wherein the wimpy device structures have a higher threshold voltage than the nominal device structures.
13. The device as recited in claim 12 , wherein the first material includes a Si 3 P 4 material.
14. The device as recited in claim 12 , wherein the wimpy device structures have a same gate length, same channel doping and same contact pitch as the nominal device structures.
15. The device as recited in claim 12 , wherein the first source/drain regions include strained material and the second source/drain regions include relaxed material due to laser selective annealing.
16. The device as recited in claim 12 , wherein the second source/drain regions include more electrically active phosphorous than the first source/drain regions due to selective laser annealing.
17. The device as recited in claim 12 , wherein the first source/drain regions and the second source/drain regions have substantially the same resistance.
18. The device as recited in claim 12 , wherein the first source/drain regions and the second source/drain regions are formed on a dielectric layer.
19. The device as recited in claim 12 , wherein the first source/drain regions transfer about half of stress introduced by the first material into channel regions.
20. The device as recited in claim 12 , wherein the first gate structure includes a first gate conductor and first spacer layers; and
the second gate structure includes a second gate conductor and second spacer layers.