Patent Assignment
Reel/Frame 052644/0868
Assignment of Assignor's Interest
Recorded: 2020-05-13
Pages: 17
Assignor
INTERNATIONAL BUSINESS MACHINES CORPORATION
Executed: 2020-03-06
Assignee
ELPIS TECHNOLOGIES INC.
1891 ROBERTSON ROAD, SUITE 100, OTTAWA, K2H 5B7, CANADA
Covered Properties
(252)
Controlled Spalling of Fine Features
Patent:
9,455,180 →
Application:
14/943,118 →
Dual Isolation Fin and Method of Making
Capacitor in Strain Relaxed Buffer
Patent:
9,570,575 →
Application:
14/974,123 →
Channel Replacement and Bimodal Doping Scheme for Bulk Finfet Threshold Voltage Modulation with Reduced Performance Penalty
Interlevel Airgap Dielectric
Nanowire Semiconductor Device
Patent:
9,613,873 →
Application:
14/978,362 →
Superlattice Lateral Bipolar Junction Transistor
Junctionless Back End of the Line via Contact
Patent:
9,536,832 →
Application:
14/983,643 →
Bottom Source/Drain Silicidation for Vertical Field-Effect Transistor (Fet)
Columnar Interconnects and Method of Making Them
Recessed Metal Liner Contact with Copper Fill
Patent:
9,496,225 →
Application:
15/018,387 →
Tunneling Fin Type Field Effect Transistor with Epitaxial Source and Drain Regions
Ion Flow Barrier Structure for Interconnect Metallization
Dual Work Function Cmos Devices
Beol Vertical Fuse Formed Over Air Gap
Patent:
9,666,528 →
Application:
15/050,975 →
Patterned Gate Dielectrics for Iii-V-Based Cmos Circuits
Contact Area Structure and Method for Manufacturing the Same
Patent:
9,576,901 →
Application:
15/053,106 →
Forming Nanotips
Well and Punch Through Stopper Formation Using Conformal Doping
Vertical Finfet with Strained Channel
Patent:
9,614,077 →
Application:
15/060,124 →
ROBUST HIGH PERFORMANCE LOW HYDROGEN SILICON CARBON NITRIDE (SiCNH) DIELECTRICS FOR NANO ELECTRONIC DEVICES
Patent:
9,735,005 →
Application:
15/067,996 →
High Performance Middle of Line Interconnects
Top Metal Contact for Vertical Transistor Structures
Patent:
9,685,409 →
Application:
15/082,150 →
Single Process for Liner and Metal Fill
Vertical Air Gap Subtractive Etch Back End Metal
Patent:
9,653,347 →
Application:
15/086,908 →
Lateral Bipolar Junction Transistor with Abrupt Junction and Compound Buried Oxide
Patent:
9,673,307 →
Application:
15/097,548 →
Forming Chamferless Vias Using Thermally Decomposable Porefiller
Patent:
9,685,366 →
Application:
15/134,534 →
Vertical Field Effect Transistors with Bottom Contact Metal Directly Beneath Fins
Patent:
9,721,845 →
Application:
15/138,651 →
Fin Patterns with Varying Spacing Without Fin Cut
Dummy Dielectric Fins for Finfets with Silicon and Silicon Germanium Channels
Contained Punch Through Stopper for Cmos Structures on a Strain Relaxed Buffer Substrate
Patent:
9,666,486 →
Application:
15/158,196 →
Fin Cut Enabling Single Diffusion Breaks
Patent:
9,589,845 →
Application:
15/161,868 →
High Density Programmable E-Fuse Co-Integrated with Vertical Fets
Patent:
9,728,542 →
Application:
15/164,420 →
Techniques for Forming FINFET Transistors with Same Fin Pitch and Different Source/Drain Epitaxy Configurations
Avoiding Gate Metal via Shorting to Source or Drain Contacts
Aligning Conductive Vias with Trenches
Patent:
9,773,700 →
Application:
15/176,286 →
Power Decoupling Attachment
Multi Time Programmable Memories Using Local Implantation in High-K/ Metal Gate Technologies
Fabrication of a Vertical Transistor with Self-Aligned Bottom Source/Drain
Forming a Stacked Capacitor
Recessed Metal Liner Contact with Copper Fill
Patent:
9,570,574 →
Application:
15/180,171 →
Channel Replacement and Bimodal Doping Scheme for Bulk Finfet Threshold Voltage Modulation with Reduced Performance Penalty
On-Chip DC-DC Power Converters with Fully Integrated GaN Power Switches, Silicon CMOS Transistors and Magnetic Inductors
Patent:
9,806,615 →
Application:
15/185,807 →
Method and Structure to Enable Dual Channel Fin Critical Dimension Control
Patent:
9,768,075 →
Application:
15/187,152 →
Reflow Enhancement Layer for Metallization Structures
Sidewall Image Transfer Structures
Selective Sputtering with Light Mass Ions to Sharpen Sidewall of Subtractively Patterned Conductive Metal Layer
Patent:
9,799,519 →
Application:
15/192,196 →
Single or Mutli Block Mask Management for Spacer Height and Defect Reduction for Beol
High Aspect Ratio Gates
Method and Structure for Forming Mosfet with Reduced Parasitic Capacitance
Vertical Transistor with Variable Gate Length
Vertical Cmos Devices with Common Gate Stacks
Aggressive Tip-to-Tip Scaling Using Subtractive Integraton
Patent:
9,793,160 →
Application:
15/201,490 →
Forming Deep Airgaps Without Flop Over
Patent:
9,837,305 →
Application:
15/202,475 →
Hybrid Interconnects and Method of Forming the Same
Patent:
9,748,173 →
Application:
15/202,656 →
Interconnect Structure and Fabrication Thereof
Patent:
9,761,484 →
Application:
15/218,322 →
Integrating Metal-Insulator-Metal Capacitors with Air Gap Process Flow
Thin Sram Cell Having Vertical Transistors
Method and Structure of Forming Low Resistance Interconnects
Fabrication of a Strained Region on a Substrate
Patent:
9,793,398 →
Application:
15/226,834 →
Heat Sink for Semiconductor Modules
Patent:
9,831,151 →
Application:
15/226,971 →
Structure and Method to Reduce Copper Loss During Metal Cap Formation
Semiconductor Device Having Multiple Thickness Oxides
Parasitic Capacitance Reducing Contact Structure in a Finfet
Passivated Germanium-on-Insulator Lateral Bipolar Transistors
Patent:
9,852,938 →
Application:
15/231,087 →
Self-Aligned Single Dummy Fin Cut with Tight Pitch
Lateral Bipolar Junction Transistor with Multiple Base Lengths
Patent:
9,761,608 →
Application:
15/236,547 →
Wimpy Device by Selective Laser Annealing
Method and Structure to Fabricate a Nanoporous Membrane
Patent:
9,768,104 →
Application:
15/242,045 →
Dense Vertical Nanosheet
Vertical Fuse Structures
Interconnect Structure
Metal Silicate Spacers for Fully Aligned Vias
Conductive Contacts in Semiconductor on Insulator Substrate
Patent:
9,685,535 →
Application:
15/260,441 →
Multi-Angled Deposition and Masking for Custom Spacer Trim and Selected Spacer Removal
Integrated Gate Driver
Patent:
9,748,281 →
Application:
15/266,414 →
Asymmetric Junction Engineering for Narrow Band Gap Mosfet
Selective Surface Modification of Interconnect Structures
Patent:
9,859,218 →
Application:
15/268,787 →
Iii-V Compound Semiconductor Channel Material Formation on Mandrel After Middle-of-the-Line Dielectric Formation
Patent:
9,627,271 →
Application:
15/271,464 →
Thin Low Defect Relaxed Silicon Germanium Layers on Bulk Silicon Substrates
Self-Aligned Spacer for Cut-Last Transistor Fabrication
Patent:
9,704,754 →
Application:
15/272,811 →
Sacrificial Cap for Forming Semiconductor Contact
Patent:
9,805,989 →
Application:
15/272,977 →
On-Chip Mim Capacitor
Patent:
9,704,856 →
Application:
15/274,621 →
Simplified Gate Stack Process to Improve Dual Channel Cmos Performance
Patent:
9,741,822 →
Application:
15/275,565 →
Semiconductor Device with Self-Aligned Carbon Nanotube Gate
Patent:
9,704,965 →
Application:
15/277,291 →
Hybridization Fin Reveal for Uniform Fin Reveal Depth Across Different Fin Pitches
Patent:
9,754,798 →
Application:
15/278,747 →
Heterogeneous Metallization Using Solid Diffusion Removal of Metal Interconnects
Patent:
9,793,206 →
Application:
15/280,518 →
Via and Chamfer Control for Advanced Interconnects
Patent:
9,691,659 →
Application:
15/282,012 →
Contact Resistance Reduction by Iii-V Ga Deficient Surface
Patent:
9,679,967 →
Application:
15/282,152 →
Shallow Trench Isolation Recess Process Flow for Vertical Field Effect Transistor Fabrication
Patent:
9,824,934 →
Application:
15/282,378 →
Finfets with Controllable and Adjustable Channel Doping
Patent:
9,741,717 →
Application:
15/289,374 →
Junctionless Back End of the Line via Contact
Nanowire Semiconductor Device
Semiconductor Device and Method of Forming the Semiconductor Device
Forming Strained Channel with Germanium Condensation
Vertical Transistor with Uniform Bottom Spacer Formed by Selective Oxidation
Patent:
9,741,626 →
Application:
15/298,966 →
Barrier Planarization for Interconnect Metallization
Patent:
9,881,833 →
Application:
15/334,796 →
Forming Self-Aligned Dual Patterning Mandrel and Non-Mandrel Interconnects
Patent:
9,659,818 →
Application:
15/336,859 →
Forming on-Chip Metal-Insulator-Semiconductor Capacitor
Patent:
9,899,372 →
Application:
15/339,164 →
Gate Height and Spacer Uniformity
Patent:
9,704,991 →
Application:
15/339,402 →
Ion Flow Barrier Structure for Interconnect Metallization
Dummy Dielectric Fins for Finfets with Silicon and Silicon Germanium Channels
Well and Punch Through Stopper Formation Using Conformal Doping
Beol Vertical Fuse Formed Over Air Gap
Resist Having Tuned Interface Hardmask Layer for Euv Exposure
Patent:
9,929,012 →
Application:
15/378,655 →
Vertical Gate-All-Around Transistor with Top and Bottom Source/Drain Epitaxy on a Replacement Nanowire, and Method of Manufacturing the Same
Hard Masks for Block Patterning
Self-Aligned Spacer for Cut-Last Transistor Fabrication
Uniform Shallow Trench Isolation
Formation of Full Metal Gate to Suppress Interficial Layer Growth
Image Transfer Using Euv Lithographic Structure and Double Patterning Process
Approach to Fabrication of an on-Chip Resistor with a Field Effect Transistor
Patent:
9,917,082 →
Application:
15/407,592 →
FORMATION OF COMMON INTERFACIAL LAYER ON Si/SiGe DUAL CHANNEL COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE
On-Chip Mim Capacitor
Micro-Led Array Transfer
Patent:
10,002,856 →
Application:
15/416,439 →
Fabrication of Vertical Fuses from Vertical Fins
Formation of Vfet and Finfet
Patent:
9,870,952 →
Application:
15/426,479 →
Shallow Trench Isolation Structures and Contact Patterning
CMOS With Middle Of Line Processing Of III-V Material On Mandrel
Low Resistance Seed Enhancement Spacers for Voidless Interconnect Structures
Removal of Trilayer Resist Without Damage to Underlying Structure
Hybridization Fin Reveal for Uniform Fin Reveal Depth Across Different Fin Pitches
Vertical Fet with Different Channel Orientations for Nfet and Pfet
Patterned Sidewall Smoothing Using a Pre-Smoothed Inverted Tone Pattern
Modulating the Microstructure of Metallic Interconnect Structures
Trench Gate First Cmos
Forming a Combination of Long Channel Devices and Vertical Transport Fin Field Effect Transistors on the Same Substrate
Wrapped Source/Drain Contacts with Enhanced Area
Forming on-Chip Metal-Insulator-Semiconductor Capacitor
Vertical Transistor Top Epitaxy Source/Drain and Contact Structure
Robust High Performance Low Hydrogen Silicon Carbon Nitride (Sicnh) Dielectrics for Nano Electronic Devices
ROBUST HIGH PERFORMANCE LOW HYDROGEN SILICON CARBON NITRIDE (SiCNH) DIELECTRICS FOR NANO ELECTRONIC DEVICES
Adhesion of Polymers on Silicon Substrates
High Aspect Ratio Gates
Fabricating Fin-Based Split-Gate High-Drain-Voltage Transistor by Work Function Tuning
Dual Isolation Fin and Method of Making
Hybridization Fin Reveal for Uniform Fin Reveal Depth Across Different Fin Pitches
Beol Vertical Fuse Formed Over Air Gap
Zinc Oxide-Based Mask For Selective Reactive Ion Etching
Sidewall Spacer with Controlled Geometry
CONTACT RESISTANCE REDUCTION BY III-V Ga DEFICIENT SURFACE
Wafer Element with an Adjusted Print Resolution Assist Feature
Resistor Fins
Patent:
10,079,229 →
Application:
15/495,197 →
Vertical Air Gap Subtractive Etch Back End Metal
Dual Channel Silicon/Silicon Germanium Complementary Metal Oxide Semiconductor Performance with Interface Engineering
Shallow Trench Isolation Recess Process Flow for Vertical Field Effect Transistor Fabrication
On-Chip Mim Capacitor
Laser Spike Annealing for Solid Phase Epitaxy and Low Contact Resistance in an Sram with a Shared Pfet and Nfet Trench
Superlattice Lateral Bipolar Junction Transistor
Superlattice Lateral Bipolar Junction Transistor
Semiconductor Device with Self-Aligned Carbon Nanotube Gate
Via and Chamfer Control for Advanced Interconnects
Lateral Bipolar Junction Transistor with Abrupt Junction and Compound Buried Oxide
Lateral Bipolar Junction Transistor with Abrupt Junction and Compound Buried Oxide
Self-Aligned Spacer for Cut-Last Transistor Fabrication
Lateral Bipolar Junction Transistor with Multiple Base Lengths
Dual Channel Cmos Having Common Gate Stacks
Simplified Gate Stack Process to Improve Dual Channel Cmos Performance
Integrated Gate Driver
Gate-Last Semiconductor Fabrication with Negative-Tone Resolution Enhancement
Fabrication of a Strained Region on a Substrate
Nanowire Semiconductor Device
Method and Structure to Enable Dual Channel Fin Critical Dimension Control
Hybrid Interconnects and Method of Forming the Same
Finfets with Controllable and Adjustable Channel Doping
Patterned Gate Dielectrics for Iii-V-Based Cmos Circuits
High Density Programmable E-Fuse Co-Integrated with Vertical Fets
Wimpy Device by Selective Laser Annealing
Finfet with Sigma Recessed Source/Drain and Un-Doped Buffer Layer Epitaxy for Uniform Junction Formation
Patent:
10,096,713 →
Application:
15/619,923 →
Cyclic Etch Process to Remove Dummy Gate Oxide Layer for Fin Field Effect Transistor Fabrication
Fin Patterns with Varying Spacing Without Fin Cut
Fin Patterns with Varying Spacing Without Fin Cut
Double Diffusion Break Gate Structure Without Vestigial Antenna Capacitance
Patent:
10,115,724 →
Application:
15/634,799 →
Field Effect Transistor Devices Having Gate Contacts Formed in Active Region Overlapping Source/Drain Contacts
Interconnect Structure and Fabrication Thereof
Multi Time Programmable Memories Using Local Implantation in High-K/ Metal Gate Technologies
Forming on-Chip Metal-Insulator-Semiconductor Capacitor with Pillars
Aligning Conductive Vias with Trenches
Aggressive Tip-to-Tip Scaling Using Subtractive Integration
Via Formation Using Directed Self-Assembly of a Block Copolymer
Wimpy Device by Selective Laser Annealing
On-Chip DC-DC Power Converters with Fully Integrated GaN Power Switches, Silicon CMOS Transistors and Magnetic Inductors
Hybridization Fin Reveal for Uniform Fin Reveal Depth Across Different Fin Pitches
Approach to Fabrication of an on-Chip Resistor with a Field Effect Transistor
Selective Surface Modification of Interconnect Structures
Semiconductor Fin Patterning Techniques to Achieve Uniform Fin Profiles for Fin Field Effect Transistors
Patent:
10,096,524 →
Application:
15/786,744 →
Cmos with Middle of Line Processing of Iii-V Material on Mandrel
Reflow Enhancement Layer for Metallization Structures
Shallow Trench Isolation Recess Process Flow for Vertical Field Effect Transistor Fabrication
Vertical Fuse Structures
Vertical Fuse Structures
Avoiding Gate Metal via Shorting to Source or Drain Contacts
Fabricating Fin-Based Split-Gate High-Drain-Voltage Transistor by Work Function Tuning
Fin-Type Fet with Low Source or Drain Contact Resistance
Wrapped Source/Drain Contacts with Enhanced Area
Shallow Trench Isolation Structures and Contact Patterning
Finfet with Sigma Recessed Source/Drain and Un-Doped Buffer Layer Epitaxy for Uniform Junction Formation
Multi-Angled Deposition and Masking for Custom Spacer Trim and Selected Spacer Removal
Multi-Angled Deposition and Masking for Custom Spacer Trim and Selected Spacer Removal
Thin SRAM Cell Having Vertical Transistors
Wafer Element with an Adjusted Print Resolution Assist Feature
Vertical Transistor Top Epitaxy Source/Drain and Contact Structure
Double Diffusion Break Gate Structure Without Vestigial Antenna Capacitance
Patent:
10,083,964 →
Application:
15/812,249 →
Self-Aligned Single Dummy Fin Cut with Tight Pitch
Dual Channel Cmos Having Common Gate Stacks
Parasitic Capacitance Reducing Contact Structure in a Finfet
Parasitic Capacitance Reducing Contact Structure in a Finfet
Parasitic Capacitance Reducing Contact Structure in a Finfet
Sacrificial Cap for Forming Semiconductor Contact
Resist Having Tuned Interface Hardmask Layer For EUV Exposure
Resist Having Tuned Interface Hardmask Layer For EUV Exposure
Approach to Fabrication of an on-Chip Resistor with a Field Effect Transistor
Superlattice Lateral Bipolar Junction Transistor
Forming a Stacked Capacitor
Techniques for Forming FINFET Transistors with Same Fin Pitch and Different Source/Drain Epitaxy Configurations
Techniques for Forming FINFET Transistors with Same Fin Pitch and Different Source/Drain Epitaxy Configurations
Low Resistance Seed Enhancement Spacers for Voidless Interconnect Structures
Method and Structure for Forming Mosfet with Reduced Parasitic Capacitance
Uniform Shallow Trench Isolation
Patterned Sidewall Smoothing Using a Pre-Smoothed Inverted Tone Pattern
Interconnect Structure
Hard Masks for Block Patterning
Thin Low Defect Relaxed Silicon Germanium Layers on Bulk Silicon Substrates
Structure and Method to Reduce Copper Loss During Metal Cap Formation
Fin Patterns with Varying Spacing Without Fin Cut
Fin Patterns with Varying Spacing Without Fin Cut
Micro-Led Array Transfer
Wimpy Device by Selective Laser Annealing
Integrating Metal-Insulator-Metal Capacitors with Air Gap Process Flow
Beol Vertical Fuse Formed Over Air Gap
Simplified Gate Stack Process to Improve Dual Channel Cmos Performance
Simplified Gate Stack Process to Improve Dual Channel Cmos Performance
High Performance Middle of Line Interconnects
Metal Silicate Spacers for Fully Aligned Vias
Fabrication of Vertical Fuses from Vertical Fins
Fabrication of a Strained Region on a Substrate
Patterned Gate Dielectrics for Iii-V-Based Cmos Circuits
Patterned Gate Dielectrics for Iii-V-Based Cmos Circuits
Asymmetric Junction Engineering for Narrow Band Gap Mosfet
Semiconductor Fin Patterning Techniques to Achieve Uniform Fin Profiles for Fin Field Effect Transistors
Semiconductor Device with Self-Aligned Carbon Nanotube Gate
Forming a Combination of Long Channel Devices and Vertical Transport Fin Field Effect Transistors on the Same Substrate
Forming a Combination of Long Channel Devices and Vertical Transport Fin Field Effect Transistors on the Same Substrate
Fabrication of a Vertical Transistor with Self-Aligned Bottom Source/Drain
Beol Vertical Fuse Formed Over Air Gap
Forming Strained Channel with Germanium Condensation
Laser Spike Annealing for Solid Phase Epitaxy and Low Contact Resistance in an Sram with a Shared Pfet and Nfet Trench
Wafer Element with an Adjusted Print Resolution Assist Feature
Finfet with Sigma Recessed Source/Drain and Un-Doped Buffer Layer Epitaxy for Uniform Junction Formation
Field Effect Transistor Devices Having Gate Contacts Formed in Active Region Overlapping Source/Drain Contacts
Modulating the Microstructure of Metallic Interconnect Structures
Field Effect Transistor Devices Having Gate Contacts Formed in Active Region Overlapping Source/Drain Contacts
Related Assignments
(21)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Nov 17, 2015
From: BEDELL, STEPHEN W.; LI, NING; LAURO, PAUL A.; SADANA, DEVENDRA K.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037056/0172 →
Assignment of Assignor's Interest
Dec 9, 2015
From: CHENG, CHENG-WEI; LEE, SANGHOON; LEOBANDUNG, EFFENDI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037246/0937 →
Assignment of Assignor's Interest
Dec 18, 2015
From: BALAKRISHNAN, KARTHIK; CHENG, KANGGUO; HASHEMI, POUYA; REZNICEK, ALEXANDER
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037326/0386 →
Assignment of Assignor's Interest
Dec 22, 2015
From: LEOBANDUNG, EFFENDI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037349/0065 →
Assignment of Assignor's Interest
Dec 22, 2015
From: BALAKRISHNAN, KARTHIK; BEDELL, STEPHEN W.; HASHEMI, POUYA; HEKMATSHOARTABARI, BAHMAN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037350/0899 →
Assignment of Assignor's Interest
Dec 30, 2015
From: LEOBANDUNG, EFFENDI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037380/0862 →
Assignment of Assignor's Interest
Jan 8, 2016
From: KARVE, GAURI; ROBISON, ROBERT R.; VEGA, REINALDO A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037440/0063 →
Assignment of Assignor's Interest
Jan 20, 2016
From: ANDERSON, BRENT A.; BU, HUIMING; HOOK, TERENCE B.; LIE, FEE LI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037565/0494 →
Assignment of Assignor's Interest
Jan 22, 2016
From: BALAKRISHNAN, KARTHIK; HASHEMI, POUYA; LEE, SANGHOON
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037555/0964 →
Assignment of Assignor's Interest
Feb 4, 2016
From: MURRAY, CONAL E.; YANG, CHIH-CHAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037664/0674 →
Assignment of Assignor's Interest
Feb 12, 2016
From: BASKER, VEERARAGHAVAN S.; LIU, ZUOGUANG; YAMASHITA, TENKO; YEH, CHUN-CHEN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037727/0726 →
Assignment of Assignor's Interest
Feb 16, 2016
From: DEMAREST, JAMES J.; KELLY, JAMES J.; MOTOYAMA, KOICHI; PENNY, CHRISTOPHER J.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037739/0929 →
Assignment of Assignor's Interest
Feb 17, 2016
From: JAGANNATHAN, HEMANTH; SANKARAPANDIAN, MUTHUMANICKAM; WATANABE, KOJI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037754/0889 →
Assignment of Assignor's Interest
Feb 23, 2016
From: BERGENDAHL, MARC A.; DEMAREST, JAMES J.; PENNY, CHRISTOPHER J.; WASKIEWICZ, CHRISTOPHER J.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037801/0372 →
Assignment of Assignor's Interest
Feb 24, 2016
From: ANDO, TAKASHI; FRANK, MARTIN M.; MO, RENEE T.; NARAYANAN, VIJAY
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037811/0108 →
Assignment of Assignor's Interest
Feb 25, 2016
From: CHENG, KANGGUO; DIVAKARUNI, RAMACHANDRA; LI, JUNTAO; MOCHIZUKI, SHOGO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037833/0810 →
Assignment of Assignor's Interest
Feb 25, 2016
From: CHEN, HSUEH-CHUNG; FAN, SU CHEN; YANG, CHIH-CHAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037827/0071 →
Assignment of Assignor's Interest
Mar 3, 2016
From: LEOBANDUNG, EFFENDI; YAMASHITA, TENKO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037881/0784 →
Corrective Assignment to Correct the Third Inventors Execution Date in the Assignment Document Previously Recorded at Reel: 037555 Frame: 0964. Assignor(S) Hereby Confirms the Assignment.
Mar 3, 2016
From: BALAKRISHNAN, KARTHIK; HASHEMI, POUYA; LEE, SANGHOON
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037985/0185 →
Assignment of Assignor's Interest
Mar 9, 2016
From: ADUSUMILLI, PRANEET; BASKER, VEERARAGHAVAN S.; BU, HUIMING; LIU, ZUOGUANG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037930/0689 →
Assignment of Assignor's Interest
Jun 29, 2016
From: CHENG, KANGGUO; KANAKASABAPATHY, SIVANANDA K.; XU, PENG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 039040/0961 →