Simplified gate stack process to improve dual channel CMOS performance
A semiconductor device and method of making the same wherein the semiconductor device includes a pFET region including a SiGe channel having a Si-rich top surface within the gate portion, and an nFET region including a Si channel. The method includes subjecting both the pFET and nFET regions to a single high-temperature anneal process thereby avoiding the need for an additional spike anneal process at RMG module.
1. A method of fabricating a semiconductor device, the method comprising:
forming a pFET region including:
a SiGe channel;
a first set of spacers extending from the top surface of the SiGe channel; and
a first dummy oxide including SiGeOx, wherein the first dummy oxide layer is positioned between the first set of spacers;
providing an nFET region including:
a Si channel;
a second set of spacers extending from the top surface of the Si channel; and
a second dummy oxide layer including SiOx, wherein the second dummy oxide layer is positioned between the second set of spacers;
annealing the pFET and the nFET region to yield a Si-rich layer on a top surface of the SiGe channel;
removing the first dummy oxide layer and the second dummy oxide layer; and
depositing a first gate material between the first set of spacers and a second gate material between the second set of spacers.
2. The method of claim 1 , wherein the annealing includes subjecting the pFET region and nFET region to a temperature of 950 to 1077° C.
3. The method of claim 1 further comprising, before depositing the first gate material, depositing a first high-k dielectric layer in contact with the spacers.
4. The method of claim 1 further comprising, before depositing the second gate material, depositing a second high-k dielectric layer in contact with the second set of spacers.
5. The method of claim 3 further comprising, before depositing the first high-k dielectric layer, exposing the Si-rich layer to ozone to form an ozone layer.
6. The method of claim 4 further comprising, before depositing the second high-k dielectric layer, exposing the top portion of the Si channel located between the second set of spacers to ozone to form an ozone layer.
7. The method of claim 5 , wherein the ozone layer is positioned between the Si-rich surface and the first high-k dielectric layer.
8. The method of claim 6 , wherein the ozone layer is positioned between the portion of the top surface of the Si channel located between the second set of spacers surface and the second high-k dielectric layer.
9. The method of claim 1 , further comprising forming source and drain regions within the nFET region and the pFET region.
10. The method of claim 1 , wherein the first high-k dielectric layer and second high-k dielectric layer are independently selected from silicon nitride, aluminum oxide, zirconium oxide, titanium oxide, tantalum pentoxide, barium-strontium-titanate, strontium-titanate-oxide, lead-zirconium-titanate, and combinations thereof.
11. The method of claim 1 , wherein the first gate material and second gate material are independently selected from TiN, TiAl, TaN, and combinations thereof.
12. The method of claim 1 , wherein the Si-rich surface has a concentration of Ge is at least 10% lower than the concentration of Ge in the SiGe channel.
13. The method of claim 1 , wherein the Si-rich surface has a concentration of Ge is at least 5% lower than the concentration of Ge in the SiGe channel.