Dual channel CMOS having common gate stacks
Embodiments are directed to a method and resulting structures for a dual channel complementary metal-oxide-semiconductor (CMOS) having common gate stacks. A first semiconductor fin is formed on a substrate. A second semiconductor fin is formed adjacent to the first semiconductor fin on the substrate. An oxide layer is formed over the first and second semiconductor fins and annealed at a temperature effective to increase a germanium concentration of the second semiconductor fin. The annealing process is selective to the second semiconductor fin and does not increase a germanium concentration of the first semiconductor fin.
1. A semiconductor device, comprising:
a first semiconductor fin on a substrate;
a second semiconductor fin adjacent to the first semiconductor fin on the substrate, said second semiconductor fin comprising a bottom portion, a middle portion, and a top portion; and
a shared conductive gate formed over a channel region of the first and second semiconductor fins;
wherein the middle portion comprises a first concentration of a first material and the top portion comprises a second concentration of the first material;
wherein the second concentration is higher than the first concentration; and
further wherein the first semiconductor fin and the bottom portion of the second semiconductor fin do not include the first material.
2. The semiconductor device of claim 1 , wherein the first material comprises germanium, the first concentration comprises 20 atomic percent, and the second concentration comprises 40 atomic percent.
3. The semiconductor device of claim 1 , wherein the shared conductive gate comprises a TiN/TiAlC/TiN gate stack.
4. A dual channel complementary metal-oxide-semiconductor (CMOS), comprising:
a first semiconductor fin comprising silicon on a substrate;
a second semiconductor fin adjacent to the first semiconductor fin on the substrate, said second semiconductor fin comprising a bottom portion, a middle portion, and a top portion; and
a shared conductive gate formed over a channel region of the first and second semiconductor fins;
wherein the bottom portion of the second semiconductor fin does not include germanium, the middle portion of the second semiconductor fin comprises a first concentration of germanium, and the top portion of the second semiconductor fin comprises a second concentration of germanium and further wherein the first concentration of germanium is less than the second concentration of germanium.
5. The semiconductor device of claim 4 , wherein the first concentration of germanium is 20 atomic percent and the second concentration of germanium is 40 atomic percent germanium.
6. The semiconductor device of claim 4 , further comprising a shallow trench isolation (STI) formed between the first and second semiconductor fins and above a surface of the bottom portion.
7. The semiconductor device of claim 4 , wherein the bottom portion comprises a thickness of about 10 nm to about 50 nm, the middle portion comprises a thickness of about 15 nm, and the top portion comprises a thickness of about 35 nm.