Via and chamfer control for advanced interconnects
Methods of forming a semiconductor structure includes etching a via opening through an interlevel dielectric to a metal conductor. A contiguous metal liner is deposited onto exposed surfaces of the substrate. The substrate is exposed to a gaseous ion plasma to remove portions of the metal liner that are horizontally oriented and to reduce a height of the metal liner from portions thereof that are vertically oriented. Subsequently, a trench opening is formed in the interlevel dielectric, wherein the trench opening is connected with the via opening, wherein at least a portion of the metal liner remains on sidewall surfaces within the via opening during the forming of the trench opening. A diffusion barrier liner is deposited within the trench opening and the via opening. A conductive material is formed within remaining portions of the trench opening and the via opening to define the interconnect structure.
1. A method of forming a semiconductor structure, the method comprising:
forming a first dielectric material including a metal conductor embedded therein on a substrate;
forming a second dielectric material above the first dielectric material and the metal conductor;
etching a via opening in the second dielectric material to the metal conductor embedded in the first dielectric material;
forming a metal liner on exposed surfaces within the via opening located in the second dielectric material;
anisotropically removing portions of the metal liner that are horizontally oriented and reducing a height of the metal liner from portions thereof that are vertically oriented;
etching a trench opening in the second dielectric material, wherein the trench opening is connected with the via opening, wherein at least a portion of the metal liner remains on sidewall surfaces within the via opening during said forming of the trench opening and is at a height about equal to a remaining thickness of the second dielectric layer underlying the trench opening.
2. The method of claim 1 , wherein exposing the substrate to the gaseous ion plasma comprises forming ions from a gas comprising argon, helium, neon, xenon, nitrogen, ammonia, forming gas, or combinations thereof.
3. The method of claim 1 , wherein said second dielectric material comprises a low dielectric constant material having a k value of less than 3.9.
4. The method of claim 1 , wherein said second dielectric material comprises silicon, carbon, and oxygen.
5. The method of claim 1 , wherein said second dielectric material comprises pores.
6. The method of claim 1 , wherein the metal liner comprises tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium nitride, ruthenium tantalum, ruthenium tantalum nitride, iridium, iridium nitride, iridium tantalum nitride, tungsten, tungsten nitride, or combinations thereof.
7. The method of claim 1 , wherein the metal liner is at a thickness within a range of 1 nanometer to 20 nanometers.
8. The method of claim 1 , further comprising forming a capping layer above said first dielectric material having said at least one conductive region embedded therein; and wherein exposing the substrate to the gaseous ion plasma to removes a portion of the capping layer at a bottom of the via opening.