Patterned sidewall smoothing using a pre-smoothed inverted tone pattern
Embodiments are directed to a method and resulting structures for smoothing the sidewall roughness of a post-etched film. A sacrificial layer is formed on a substrate. A patterned mask is formed by removing portions of the sacrificial layer to expose a surface of the substrate. The sidewalls of the patterned mask are smoothed and a target layer is formed over the patterned mask and the substrate. Portions of the target layer are removed to expose a surface of the patterned mask and the patterned mask is removed.
1. A method for forming a semiconductor device, the method comprising:
forming a sacrificial layer on a substrate;
forming a patterned mask by removing portions of the sacrificial layer to expose a surface of the substrate, thereby forming one or more cavities in the sacrificial layer at one or more locations where the surface of the substrate is exposed;
smoothing sidewalls of the patterned mask;
forming a target layer over the patterned mask and the substrate, such that the target layer completely fills in the one or more cavities;
removing portions of the target layer to expose a surface of the patterned mask; and
removing the patterned mask.
2. The method of claim 1 , wherein after smoothing the sidewalls of the patterned mask each sidewall of the patterned mask comprises a one sigma root-mean-square (RMS) roughness of less than about 10 atomic layers, or less than about 3 nm.
3. The method of claim 1 , wherein after smoothing the sidewalls of the patterned mask each sidewall of the patterned mask comprises a one sigma root-mean-square (RMS) roughness of less than about 3 atomic layers, or less than about 1 nm.
4. The method of claim 1 , wherein smoothing sidewalls of the patterned mask comprises a high temperature furnace annealing or a hot mold embossing process at a temperature of greater than about 500 degrees Celsius.
5. The method of claim 1 , wherein after removing the patterned mask each sidewall of the target layer comprises a one sigma root-mean-square (RMS) roughness of less than about 10 atomic layers, or less than about 3 nm.
6. The method of claim 1 , wherein after removing the patterned mask each sidewall of the target layer comprises a one sigma root-mean-square (RMS) roughness of less than about 3 atomic layers, or less than about 1 nm.
7. The method of claim 1 , wherein removing the patterned mask comprises an etch selective to the target layer.
8. A method for forming a semiconductor device, the method comprising:
forming a sacrificial layer on a substrate;
forming a patterned mask by removing portions of the sacrificial layer to expose a surface of the substrate;
smoothing sidewalls of the patterned mask;
forming a semiconductor layer over the patterned mask and the substrate;
forming a semiconductor fin by removing portions of the semiconductor layer to expose a surface of the patterned mask;
removing the patterned mask; and
forming a gate over a channel region of the semiconductor fin.
9. The method of claim 8 , wherein smoothing sidewalls of the patterned mask comprises a high temperature furnace annealing or a hot mold embossing process at a temperature of greater than about 500 degrees Celsius.
10. The method of claim 8 , wherein a sidewall angle of the semiconductor fin after removing the patterned mask is greater than about 90 degrees as measured from a top surface of the semiconductor fin.
11. The method of claim 8 , wherein after removing the patterned mask each sidewall of the semiconductor fin comprises a one sigma root-mean-square (RMS) roughness of less than about 10 atomic layers, or less than about 3 nm.
12. The method of claim 8 , wherein after removing the patterned mask each sidewall of the semiconductor fin comprises a one sigma root-mean-square (RMS) roughness of less than about 3 atomic layers, or less than about 1 nm.
13. The method of claim 8 , wherein removing the patterned mask comprises an etch selective to the semiconductor fin.
14. The method of claim 8 , wherein the semiconductor fin comprises silicon germanium (SiGe).
15. The method of claim 14 further comprising forming a doped region on the semiconductor fin and adjacent to the gate; wherein the doped region comprises p-type dopants selected from the group consisting of gallium (Ga), boron (B), difluoroboron (BF2), and aluminum (Al).