Dual isolation fin and method of making
A method of making a dual isolation fin comprises applying a mask to a substrate and etching the exposed areas of the substrate to form a mandrel; forming a dielectric layer on the surface of the substrate and adjacent to the mandrel; forming a first epitaxially formed material on the exposed portions of the mandrel; forming a second epitaxially formed material on the first epitaxially formed material; forming a first isolation layer on the dielectric layer and adjacent to the second epitaxially formed material; removing the mask and mandrel after forming the first isolation layer; removing the first epitaxially formed material after removing the mask and mandrel; and forming a second isolation layer.
1. A semiconductor structure comprising:
a substrate;
a fin of a second epitaxially formed material provided on a dielectric layer provided on the substrate, a first isolation region on the dielectric layer and adjacent a fin sidewall, and a second isolation region adjacent another fin sidewall including a bottom portion in contact with the substrate by:
applying a mask to portions of the substrate and etching exposed areas of the substrate to form a mandrel;
forming the dielectric layer disposed on a surface of the substrate and adjacent to the mandrel;
forming a first epitaxially formed material on an exposed portion of the mandrel;
forming the second epitaxially formed material on the first epitaxially formed material;
forming a first isolation layer on top of the dielectric layer and adjacent to the second epitaxially formed material;
removing the mask and mandrel after forming the first isolation layer to form an open area of the substrate;
removing the first epitaxially formed material after removing the mask and mandrel; and
forming a second isolation layer in the open area of the substrate such that the second isolation layer is formed on a sidewall and directly on a portion of a top surface of the dielectric layer;
wherein:
the first isolation layer has a thickness equal to a height of the second epitaxially formed material; and
wherein the second epitaxially formed material has fewer defects relative to forming the second epitaxially formed material without the first epitaxially formed material.
2. The semiconductor structure of claim 1 , wherein the substrate comprises silicon.
3. The semiconductor structure of claim 1 , wherein:
applying the mask to portions of the substrate and etching exposed areas of the substrate to form the mandrel comprises forming the mandrel with a height of between 50 to 200 nanometers.
4. The semiconductor structure of claim 1 , wherein the dielectric layer has a thickness of 30 to 100 nanometers.
5. The semiconductor structure of claim 1 , wherein the second epitaxially formed material has a thickness less than or equal to 30 nanometers.
6. The semiconductor structure of claim 1 , wherein the second epitaxially formed material has a thickness of 3 to 10 nanometers.
7. The semiconductor structure of claim 1 , wherein the first isolation layer has a thickness less than a height of the second epitaxially formed material.
8. The semiconductor structure of claim 1 , wherein the first isolation layer and the dielectric layer comprise a same material.
9. The semiconductor structure of claim 1 , wherein:
the first epitaxially formed material comprises a first III-V material.
10. The semiconductor structure of claim 9 , wherein the second epitaxially formed material comprises a second III-V material.
11. The semiconductor structure of claim 1 , wherein the first III-V material has a lattice constant greater than a lattice constant of silicon and less than a lattice constant of the second III-V material.
12. The semiconductor structure of claim 1 , wherein the first isolation layer and the second isolation layer comprise a same material.
13. The semiconductor structure of claim 1 , wherein the first isolation layer and the second isolation layer comprise a different material.