CMOS with middle of line processing of III-V material on mandrel

1. A method, comprising:

forming first structures on a first portion of a silicon substrate and second structures on a second portion of the silicon substrate;

forming spacers on the first structures;

forming dummy gates on the first structures and on the second structures;

depositing a first interlayer dielectric on the formed dummy gates in the first portion and the second portion;

removing the dummy gates from the second structures;

forming one or more second metal gates on the second structures;

performing an anneal on the silicon substrate, the first structures, and the second structures;

forming recess areas in the first interlayer dielectric to expose the first structures;

removing the spacers from the first structures;

epitaxially growing sidewalls on the first structures;

removing portions of the first structures outside the dummy gates from the first portion;

depositing a second interlayer dielectric on the first portion;

removing the dummy gates from the first portion;

removing portions of the first structures previously under the dummy gates from the first portion; and

forming one or more first metal gates on the first structures.

2. The method of claim 1 , wherein the first portion of the silicon substrate comprises silicon-on-insulator and wherein the second portion of the silicon substrate comprises silicon-on-insulator or SiGe.

3. The method of claim 1 , wherein performing an anneal on the silicon substrate, the first structures, and the second structures comprises performing a high-k reliability anneal.

4. The method of claim 1 , wherein epitaxially growing sidewalls on the first structures comprises epitaxially growing a III-V material on the first structures after the anneal.

5. The method of claim 1 , wherein epitaxially growing sidewalls on the first structures comprises epitaxially growing InGaAs on the first structures after the anneal.

6. A method, comprising:

providing a silicon substrate, a buried oxide layer on the silicon substrate, an NFET layer of silicon-on-insulator on an NFET portion of the buried oxide layer, and a PFET layer of silicon-on-insulator or SiGe on a PFET portion of the buried oxide layer;

forming mandrels in the silicon-on-insulator of the NFET layer;

forming fins in the silicon-on-insulator or SiGe of the PFET layer;

forming first spacers on the mandrels;

forming dummy gates on the mandrels and on the fins;

depositing a first interlayer dielectric on the formed dummy gates in the NFET portion and the PFET portion;

removing the dummy gates from the fins;

forming one or more metal gates on the fins;

performing an anneal on the silicon substrate, the mandrels, and the fins;

forming recess areas in the first interlayer dielectric to expose the mandrels;

removing the first spacers;

epitaxially growing sidewalls on the mandrels;

removing portions of the mandrels outside the dummy gates from the NFET portion;

depositing a second interlayer dielectric on the NFET portion;

removing the dummy gates from the NFET portion;

removing remaining portions of the mandrels from the NFET portion to leave the sidewalls grown on the mandrels; and

forming one or more metal gates on the sidewalls grown on the removed mandrels.

7. The method of claim 6 , further comprising patterning the NFET portion using an oxide hardmask prior to forming the mandrels in the silicon-on-insulator of the NFET layer.

8. The method of claim 6 , further comprising patterning the PFET portion using a sidewall image transfer technique prior to forming the fins in the silicon-on-insulator or SiGe of the PFET layer.

9. The method of claim 6 , wherein forming the first spacers on the mandrels comprises depositing a conformal nitride or an oxide on the mandrels using a sidewall image transfer technique.

10. The method of claim 9 , wherein the conformal nitride or oxide on the mandrels is etched to form a structure defining the spacer using reactive ion etching.

11. The method of claim 6 , further comprising planarizing after depositing the first interlayer dielectric.

12. The method of claim 6 , wherein forming the recess areas in the first interlayer dielectric to expose the mandrels comprises using a dry etch process, a wet etch process, or a combination of dry etch and wet etch processes.

13. The method of claim 6 , wherein epitaxially growing the sidewalls on the mandrels comprises seeding the mandrels with a III-V material and maintaining a preselected temperature and pressure to initiate a growth of the III-V material.

14. The method of claim 6 , wherein removing the portions of the mandrels outside the dummy gates from the NFET portion comprises exposing at least an upper portion of the buried oxide layer on the NFET portion.

15. The method of claim 6 , further comprising forming second spacers transverse to the sidewalls after removing the portions of the mandrels from outside the dummy gates on the NFET portion.

16. The method of claim 6 , further comprising epitaxially growing source/drains in the PFET layer after forming dummy gates on the mandrels and on the fins and epitaxially growing source/drains in the NFET layer after removing the portions of the mandrels from outside the dummy gates on the NFET portion.