FinFETs with controllable and adjustable channel doping
A method of forming features of a finFET structure includes forming fins on a surface of a substrate. A first liner is formed around each fin and a shallow trench isolation region is formed around each fin. A dopant layer is implanted in each fin. A portion of the shallow trench isolation region is etched from each fin. A first portion of the structure is blocked and the first liner replaced with a second liner in a second portion of the structure.
1. A method of forming features of a finFET structure, comprising:
forming fins on a surface of a substrate;
forming a first liner around each fin;
forming a shallow trench isolation region around each fin;
implanting a dopant layer in each fin;
etching a portion of the shallow trench isolation region from each fin;
blocking a first portion of the structure and replacing the first liner with a second liner in a second portion of the structure; and
annealing the structure to drive the dopants in the dopant layer into the second liner.
2. The method of claim 1 , wherein the first liner and the second liner comprise a different material.
3. The method of claim 1 , wherein the first liner comprises a material selected from nitride, nitride oxide, or a combination comprising at least one of the foregoing.
4. The method of claim 1 , wherein the second liner comprises an oxide.
5. The method of claim 4 , wherein the second liner comprises silicon dioxide.
6. The method of claim 1 , wherein the second liner is formed onto the structure with by a method selected from chemical vapor deposition, plasma deposition, physical vapor deposition, atomic layer deposition or a combination comprising at least one of the foregoing.
7. The method of claim 6 , wherein the method is plasma enhanced chemical vapor deposition.
8. The method of claim 1 , wherein the first portion comprises a high threshold voltage region of the structure.
9. The method of claim 1 , wherein the second portion comprises a low threshold voltage region of the structure.
10. The method of claim 1 , wherein the annealing occurs at a temperature of less than or equal to 900° C.
11. The method of claim 1 , further comprising stripping a dummy gate, the first liner, and the second liner from the structure, forming a replacement metal gate and further processing the structure.
12. A finFET structure, comprising:
a plurality of fins located on a surface of a substrate;
a first liner disposed around each fin in a high threshold voltage region of the structure, with a dopant layer implanted into each fin; and
a second liner disposed around each fin in a low threshold voltage region of the structure, with a dopant layer implanted into each fin;
wherein the first liner and the second liner comprise different materials, and wherein the second liner comprises dopants from the dopant layer.
13. The finFET structure of claim 12 , wherein the first liner comprises a nitride.
14. The finFET structure of claim 12 , wherein the second liner comprises an oxide.
15. The finFET structure of claim 14 , wherein the second liner comprises silicon dioxide.
16. The finFET structure of claim 12 , wherein an upper portion of the fins in the first region comprise a substantially low concentration dopants from the dopant layer.
17. A method of forming features of a finFET structure, comprising:
forming fins on a surface of a substrate;
forming a first liner comprising a nitride around each fin;
forming a shallow trench isolation region around each fin;
removing a fin from the structure;
implanting a dopant layer in each fin;
etching a portion of the shallow trench isolation region from each fin;
blocking a high threshold voltage region of the structure and replacing the first liner with a second liner comprising an oxide in a low threshold voltage region of the structure;
forming a dummy gate and spacers over a fin;
performing a source/drain epitaxy to form the finFET structure; and
annealing the structure to drive the dopants in the dopant layer into the second liner.