IP Library Granted Patent US 9,704,965
Granted Patent B1
US 9,704,965 · App. 15/277,291 · Granted Jul 11, 2017

Semiconductor device with self-aligned carbon nanotube gate

Inventors: Qing Cao (Yorktown Heights, NY); Shu-Jen Han (Cartlandt Manor, NY); Ning Li (White Plains, NY); Jianshi Tang (Elmsford, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L29/4966H01L21/26513H01L21/28088H01L21/32056H01L29/0847H01L29/517H01L29/6656H01L29/66568H01L29/78
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Quick Facts
Patent No.
US 9,704,965
App. No.
15/277,291
Granted
Jul 11, 2017
Kind
B1
Abstract

A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.

Claims (37)

1. A method for forming a semiconductor device, the method comprising:

forming a channel layer on a substrate;

depositing a gate dielectric on the channel layer;

patterning a mask on the gate dielectric;

removing an exposed portion of the gate dielectric to expose a first source/drain region and a second source/drain region of the channel layer;

forming a first source/drain contact on the first source/drain region and a second source/drain contact on the second source/drain region;

forming a cap layer over the first source/drain contact and the second source/drain contact;

removing the mask;

forming spacers adjacent to sidewalls of the first source/drain contact and the second source/drain contact;

forming an oxide region in the cap layer; and

depositing a carbon material on an exposed portion of the gate dielectric.

2. The method of claim 1 , wherein the forming spacers adjacent to sidewalls of the source/drain contacts comprises:

depositing a layer of spacer material on exposed portions of the gate dielectric, the first source/drain contact, the second source/drain contact, and the cap layer; and

removing portions of the layer of spacer material to form the spacers.

3. The method of claim 2 , wherein the spacers are arranged on the gate dielectric.

4. The method of claim 1 , wherein the carbon material partially forms a gate stack on the gate dielectric.

5. The method of claim 1 , wherein the carbon material includes a carbon nanotube.

6. The method of claim 5 , wherein the carbon nanotube is formed by a chemically self-assembled carbon nanotube formation process.

7. The method of claim 1 , wherein the gate dielectric comprises HfO 2 .

8. The method of claim 2 , wherein the layer of spacer material comprises an oxide material.

9. The method of claim 1 , further comprising: implanting ions on the first source/drain region and the second source/drain region after removing the exposed part of the gate dielectric.

10. A method for forming a semiconductor device, the method comprising:

forming a channel layer on a substrate;

depositing a gate dielectric on the channel layer;

patterning a mask on the gate dielectric;

removing an exposed portion of the gate dielectric to expose a first source/drain region and a second source/drain region of the channel layer;

forming a first source/drain contact on the first source/drain region and a second source/drain contact on the second source/drain region;

forming a cap layer over the first source/drain contact and the second source/drain contact;

removing the mask;

forming spacers adjacent to sidewalls of the first source/drain contact and the second source/drain contact;

forming an oxide region in a portion of the cap layer; and

depositing a carbon material on an exposed portion of the gate dielectric.

11. The method of claim 10 , wherein the forming spacers adjacent to sidewalls of the source/drain contacts comprises:

depositing a layer of spacer material on exposed portions of the gate dielectric, the first source/drain contacts, the second source/drain contacts, and the cap layer;

removing portions of the layer of spacer material to form the spacers.

12. The method of claim 10 , wherein the carbon material includes a carbon nanotube.

13. The method of claim 12 , wherein the carbon nanotube is formed by a chemically self-assembled carbon nanotube formation process.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052644/0868 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2016
From: CAO, QING; HAN, SHU-JEN; LI, NING; TANG, JIANSHI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 039867/0192 →