Trench gate first CMOS

1. A method of forming a semiconductor structure comprising:

forming an interlevel dielectric (ILD) layer over a semiconductor material portion located on a substrate, wherein an entirety of the semiconductor material portion is covered by the ILD layer and wherein the semiconductor material portion is a semiconductor fin or a semiconductor nanowire;

forming a gate trench extending through the ILD layer, wherein a channel region of the semiconductor material portion is exposed by the gate trench;

forming a gate stack within the gate trench and on the channel region of the semiconductor material portion, wherein the gate stack comprises a gate dielectric and a gate electrode, wherein a topmost surface of the gate dielectric is coplanar with a topmost surface of the gate electrode;

forming source/drain contact openings extending through the ILD layer to expose portions of the semiconductor material portion located on opposite sides of the gate stack, wherein each of said source/drain contact openings physically exposes an entirety of a vertical sidewall of the gate dielectric of the gate stack;

forming, after the forming of the gate stack and the source/drain contact openings, a sidewall spacer in each of the source/drain contact openings, wherein the sidewall spacer directly contacts the entirety of the vertical sidewall of the gate dielectric of the gate stack;

forming epitaxial semiconductor regions on the exposed portions of the semiconductor material portion; and

forming source/drain contact structures on the epitaxial semiconductor regions to completely fill the source/drain contact openings.

2. The method of claim 1 , wherein the sidewall spacer laterally surrounds one of the epitaxial semiconductor regions and one of the source/drain contact structures.

3. The method of claim 1 , wherein the forming the sidewall spacer comprises:

depositing a dielectric material on bottom surfaces and sidewall surfaces of the source/drain contact openings, top surfaces and sidewall surfaces of the exposed portions of the semiconductor material portion located on the opposite sides of the gate stack, and a top surface of the ILD layer;

removing horizontal portions of the deposited dielectric material; and

removing vertical portions of the deposited dielectric material present on the sidewall surfaces of the exposed portions of the semiconductor material portion located on the opposite sides of the gate stack.

4. The method of claim 1 , further comprising forming the semiconductor material portion, wherein the forming of the semiconductor portion is performed prior to the forming of the interlevel dielectric (ILD) layer over the semiconductor material portion.

5. The method of claim 4 , wherein the forming the semiconductor material portion comprises:

forming a photoresist layer on a top semiconductor layer of a semiconductor-on-insulator substrate; and

patterning the top semiconductor layer, wherein a remaining portion of the top semiconductor layer constitutes the semiconductor material portion.

6. The method of claim 5 , further comprising forming a dielectric cap layer on the top semiconductor layer.

7. The method of claim 6 , further comprising patterning the dielectric cap layer to form a dielectric cap on top of the semiconductor material portion, wherein the ILD layer covers the dielectric cap, and wherein the gate trench and the source/drain contact openings extend through the dielectric cap layer.

8. The method of claim 1 , wherein the gate stack further comprises a gate cap present on the topmost surface of both the gate dielectric and the gate electrode.

9. The method of claim 8 , wherein the forming the gate stack comprises:

forming a gate dielectric layer on physically exposed surfaces of the gate trench, the channel region of the semiconductor material portion and the ILD layer;

forming a gate electrode layer on the gate dielectric layer to completely fill the gate trench;

removing portions of the gate electrode layer and the gate dielectric layer from a top surface of the ILD layer;

recessing the gate electrode layer and the gate dielectric layer below the top surface of the ILD layer to form the gate dielectric and the gate electrode; and

filling a void that is formed on the gate dielectric and gate electrode with a dielectric material to form the gate cap.

10. The method of claim 1 , wherein the forming the source/drain contact openings is performed by an anisotropic etch.

11. The method of claim 1 , wherein the forming the epitaxial semiconductor regions are performed by a selective epitaxial growth.

12. The method of claim 1 , wherein the epitaxial semiconductor regions comprise a doped semiconductor material.

13. The method of claim 12 , further comprising diffusing dopants from the epitaxial semiconductor regions into the exposed portions of the semiconductor material potion to form doped semiconductor regions within the semiconductor material portion, wherein the doped semiconductor regions laterally surround the channel region.

14. The method of claim 13 , wherein the diffusing the dopants is performed by an anneal process.

15. The method of claim 1 , wherein topmost surfaces of the source/drain contact structures are coplanar with a topmost surface of the ILD layer and a top surface of the gate cap.

16. The method of claim 1 , wherein the substrate comprises a handle substrate and a buried insulator layer overlying the handle substrate, wherein a bottom surface of the semiconductor material portion is in direct contact with the buried insulator layer.

17. The method of claim 1 , wherein the ILD layer comprises a low-k dielectric material.

18. A method of forming a semiconductor structure comprising:

forming an interlevel dielectric (ILD) layer over a planar active region of a semiconductor material layer, wherein an entirety of the planar active region of the semiconductor material layer is covered by the ILD layer;

forming a gate trench extending through the ILD layer, wherein a channel region of the planar active region of the semiconductor material layer is exposed by the gate trench;

forming a gate stack within the gate trench and on the channel region of the planar active region of the semiconductor material layer, wherein the gate stack comprises a gate dielectric and a gate electrode, wherein a topmost surface of the gate dielectric is coplanar with a topmost surface of the gate electrode;

forming source/drain contact openings extending through the ILD layer to expose portions of the planar active region of the semiconductor material layer located on opposite sides of the gate stack, wherein each of said source/drain contact openings physically exposes an entirety of a vertical sidewall of the gate dielectric of the gate stack;

forming, after the forming of the gate stack and the source/drain contact openings, a sidewall spacer in each of the source/drain contact openings, wherein the sidewall spacer directly contacts the entirety of the vertical sidewall of the gate dielectric of the gate stack;

forming epitaxial semiconductor regions on the exposed portions of the planar active region of the semiconductor material layer; and

forming source/drain contact structures on the epitaxial semiconductor regions to completely fill the source/drain contact openings.