Tunneling fin type field effect transistor with epitaxial source and drain regions

1. A method for forming a semiconductor device comprising:

forming gate structures on sidewalls for each of at least two mandrels, wherein the gate structures are formed over channel regions of at least one fin structure;

removing the at least two mandrels to provide two sets of exposed gate structures, a first set of gate structures having a first pitch and a second set of gate structure spacers having a second pitch;

forming a first conductivity type epitaxial semiconductor material on source and drain portions of the at least one fin structure;

forming masking filling a first space between adjacent gate structures having the first pitch;

removing the first conductivity type epitaxial semiconductor material from a second space between the second set of gate structure spacers having the second pitch; and

forming a second conductivity type epitaxial semiconductor material in the second space.

2. The method of claim 1 , wherein forming the fin structures are formed using spacer image transfer.

3. The method of claim 1 , wherein said forming the gate structures comprises:

depositing a material layer for said at least two mandrels;

forming an etch mask on the material layer, wherein a width of the etch mask dictates the first pitch;

etching the material layer selectively to the etch mask to provide the at least two mandrels;

depositing a conformal material layer for the gate structures on vertically orientated and horizontally orientated surfaces of the at least two mandrels; and

etching the conformal material layer with an anisotropic etch, wherein remaining portions of the conformal material layer are present on the vertically orientated surfaces of the at least two mandrels to provide the gate structures.

4. The method of claim 3 , wherein a space between adjacent gate structure formed on separate mandrels provides the first pitch.

5. The method of claim 1 , wherein a width of a mandrel of said at least two mandrels provides the second pitch that is greater than the first pitch.

6. The method of claim 1 further comprising forming a gate sidewall spacer on sidewalls of the gate structures.

7. The method of claim 1 , wherein said forming the first conductivity type epitaxial semiconductor material on the source and drain portions of the at least one fin structure provides p-type conductivity silicon and germanium containing material.

8. The method of claim 1 , wherein said forming the masking filling the first space between the adjacent set of gate structures having the first pitch comprises depositing a dielectric material to pinch off the first space, and an etch process to remove the masking for the second space.

9. The method of claim 1 , wherein said removing the first conductivity type epitaxial semiconductor material from the second space between the second set of gate structure spacers having the second pitch comprises selective etching.

10. The method of claim 1 , wherein said second conductivity type epitaxial semiconductor material comprises an n-type silicon containing semiconductor material.

11. A method for forming the semiconductor device comprising:

forming at least two mandrels on at least one fin structure;

forming gate structure spacers on sidewalls for each of the at least two mandrels;

removing the at least two mandrels to provide two sets of gate structure spacers, a first set of gate structure spacers having a first pitch and a second set of gate structure spacers having a second pitch;

forming a first conductivity type epitaxial semiconductor material on source and drain portions of the at least one fin structure;

forming a dielectric material filling a first space between the first set of gate structure spacers having the first pitch;

removing the first conductivity type epitaxial semiconductor material from a second space between the second set of gate structure spacers having the second pitch;

forming a second conductivity type epitaxial semiconductor material in the second space; and

replacing the gate structure spacers with functional gate structures.

12. The method of claim 11 , wherein said forming the gate structures comprises:

depositing a material layer for said at least two mandrels;

forming an etch mask on the material layer, wherein a width of the etch mask dictates the first pitch;

etching the material layer selectively to the etch mask to provide the at least two mandrels;

depositing a conformal material layer for the gate structures on vertically orientated and horizontally orientated surfaces of the at least two mandrels; and

etching the conformal material layer with an anisotropic etch, wherein remaining portions of the conformal material layer are present on the vertically orientated surfaces of the at least two mandrels to provide the gate structures.

13. The method of claim 12 , wherein a space between adjacent gate structure formed on separate mandrels provides the first pitch.

14. The method of claim 11 , wherein a width of a mandrel of said at least two mandrels provides the second pitch that is greater than the first pitch.

15. The method of claim 11 , wherein said forming the first conductivity type epitaxial semiconductor material on the source and drain portions of the at least one fin structure provides p-type conductivity silicon and germanium containing material, and said second conductivity type epitaxial semiconductor material comprises an n-type silicon containing semiconductor material.