Single process for liner and metal fill
After forming a contact opening in a dielectric material layer located over a substrate, a metal liner layer comprising a nitride of an alloy and a metal contact layer comprising the alloy that provides the metal liner layer are deposited in-situ in the contact opening by sputter deposition in a single process and without an air break. Compositions of the metal liner layer and the metal contact layer can be changed by varying gas compositions employed in the sputtering process.
1. A semiconductor structure comprising a gate structure, the gate structure comprising:
a gate dielectric located along inner sidewalls of a gate spacer and a top surface and sidewalls of a channel region of a semiconductor fin located over a substrate;
a workfunction metal liner located on, and in direct physical contact with, the gate dielectric;
a first metal liner located on, and in direct physical contact with, the workfunction metal liner;
a second metal liner located on, and in direct physical contact with, the first metal liner; and
a metal gate electrode located on, and in direct physical contact, with the second metal liner, wherein the metal gate electrode is composed entirely of an alloy selected from the group consisting of MgAl, MgTi, MgV and AlV, the first metal liner is composed entirely of a carbide of the alloy that forms the metal gate electrode and the second metal liner is composed entirely of a nitride of the alloy that forms the metal gate electrode.
2. The semiconductor structure of claim 1 , wherein the work function metal liner comprises TiN.
3. The semiconductor structure of claim 1 , wherein the gate dielectric comprises HfO 2 , ZrO 2 , La 2 O 3 , Al 2 O 3 , TiO 2 , SrTiO 3 , LaAlO 3 , Y2O 3 , HfON y , ZrON y , La 2 O x N y , Al 2 O x N y , TiO x N y , SrTiO x N y , LaAlO x N y , Y 2 O x N y , SiON, SiN X , a silicate thereof or an alloy thereof, wherein x is from 0.5 to 3 and y is from 0 to 2.
4. The semiconductor structure of claim 1 , further comprising source/drain regions located on opposite sides of the gate structure.
5. The semiconductor structure of claim 4 , wherein the source/drain regions comprise fin source/drain regions located within portions of the semiconductor fin laterally surrounding the channel region, and epitaxial source/drain regions located over the fin source/drain regions.
6. The semiconductor structure of claim 4 , further comprising an interlevel dielectric (ILD) layer located over the substrate and the source/drain regions to laterally surround the gate structure.
7. The semiconductor structure of claim 5 , wherein the gate spacer contacts topmost surfaces of the fin source/drain regions.
8. The semiconductor structure of claim 6 , wherein the ILD layer has a top surface that is coplanar with a top surface of the gate spacer.
9. The semiconductor structure of claim 6 , wherein the ILD layer contacts outer sidewalls of the gate spacer.
10. The semiconductor structure of claim 1 , wherein the substrate comprises a handle substrate and an insulator layer located over the handle substrate, wherein the semiconductor fin is in direct contact with the insulator layer.
11. The semiconductor structure of claim 1 , wherein each of the first metal liner and the second metal liner is U-shaped.
12. The semiconductor structure of claim 10 , wherein the metal gate electrode is surrounded by the second metal liner.