Sacrificial cap for forming semiconductor contact
A method for forming a semiconductor device includes forming a fins on a substrate, forming a sacrificial gate stack over a channel region of the fins, a source/drain region with a first material on the fins, a first cap layer with a second material over the source/drain region, and a second cap layer with a third material on the first cap layer. A dielectric layer is deposited over the second cap layer. The sacrificial gate stack is removed to expose a channel region of the fins. A gate stack is formed over the channel region of the fins. A portion of the dielectric layer is removed to expose the second cap layer. The second cap layer and the first cap layer are removed to expose the source/drain region. A conductive material is deposited on the source/drain region.
1. A method for forming a semiconductor device, the method comprising:
forming a first fin and a second fin on a substrate;
forming a sacrificial gate stack over a channel region of the first fin and a channel region of the second fin;
forming a source/drain region with a first material on the first fin and the second fin;
forming a first cap layer with a second material over the source/drain region;
forming a second cap layer with a third material on the first cap layer;
depositing a dielectric layer over the second cap layer;
removing the sacrificial gate stack to expose a channel region of the first fin;
forming a gate stack over the channel region of the first fin;
removing a portion of the dielectric layer to expose the second cap layer;
selectively removing the second cap layer and the first cap layer to expose the source/drain region; and
depositing a conductive material on the source/drain region.
2. The method of claim 1 , further comprising forming a trench isolation region adjacent to the first fin.
3. The method of claim 1 , wherein the forming the source/drain region with the first material includes epitaxially growing the first material on the first fin and the second fin.
4. The method of claim 1 , wherein the first material includes a doped semiconductor material.
5. The method of claim 1 , wherein the first cap layer is formed by an epitaxial growth process.
6. The method of claim 1 , wherein the second material includes an undoped semiconductor material.
7. The method of claim 1 , wherein the first material is dissimilar from the second material.
8. The method of claim 1 , wherein the third material includes an insulator material.
9. The method of claim 1 , wherein the third material includes an nitride material.
10. The method of claim 1 , further comprising forming spacers adjacent to the sacrificial gate stack.
11. The method of claim 1 , further comprising forming a silicide material on the source/drain region prior to depositing the conductive material.
12. A method for forming a semiconductor device, the method comprising:
forming a first fin and a second fin on a substrate;
forming a sacrificial gate stack over a channel region of the first fin and a channel region of the second fin;
forming a source/drain region with a first material on the first fin and the second fin, wherein forming the source/drain region includes forming a connection between the first fin and the second fin with the first material;
forming a first cap layer with a second material over the source/drain region;
forming a second cap layer with a third material on the first cap layer;
depositing a dielectric layer over the second cap layer;
removing the sacrificial gate stack to expose a channel region of the first fin;
forming a gate stack over the channel region of the first fin;
removing a portion of the dielectric layer to expose the second cap layer;
selectively removing the second cap layer and the first cap layer to expose the source/drain region; and
depositing a conductive material on the source/drain region.
13. A method for forming a semiconductor device, the method comprising:
forming a first fin and a second fin on a substrate;
forming a sacrificial gate stack over a channel region of the first fin and a channel region of the second fin;
forming a source/drain region with a first material on the first fin and the second fin;
forming a first cap layer with a second material over the source/drain region, wherein the first cap layer forms a connection between the source/drain region on the first fin and the source/drain region on the second fin;
forming a second cap layer with a third material on the first cap layer;
depositing a dielectric layer over the second cap layer;
removing the sacrificial gate stack to expose a channel region of the first fin;
forming a gate stack over the channel region of the first fin;
removing a portion of the dielectric layer to expose the second cap layer;
selectively removing the second cap layer and the first cap layer to expose the source/drain region; and
depositing a conductive material on the source/drain region.
14. The method of claim 13 , further comprising forming a trench isolation region adjacent to the first fin.
15. The method of claim 13 , wherein the forming the source/drain region with the first material includes epitaxially growing the first material on the first fin and the second fin.
16. The method of claim 13 , wherein the first material includes a doped semiconductor material.
17. The method of claim 13 , wherein the first cap layer is formed by an epitaxial growth process.
18. The method of claim 13 , wherein the second material includes an undoped semiconductor material.
19. The method of claim 13 , wherein the first material is dissimilar from the second material.
20. The method of claim 13 , wherein the third material includes an insulator material.