Nanowire semiconductor device
A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a <110> orientation wherein the hard mask is oriented in the <112> direction, etching the silicon substrate to form a mandrel having (111) faceted sidewalls; forming a layer of insulator material on the substrate; forming a sacrificial stack comprising alternating layers of sacrificial material and dielectric material disposed on the layer of insulator material and adjacent to the mandrel; patterning and etching the sacrificial stack to form a modified sacrificial stack adjacent to the mandrel and extending from the mandrel; removing the sacrificial material from the modified sacrificial stack to form growth channels; epitaxially forming semiconductor in the growth channels; and etching the semiconductor to align with the end of the growth channels and form a semiconductor stack comprising alternating layers of dielectric material and semiconductor material.
1. A method for forming a nanowire device, the method comprising:
depositing a hard mask on portions of a silicon substrate having a <110> orientation wherein the hard mask is oriented in the <112> direction;
etching the silicon substrate to form a mandrel having (111) faceted sidewalls and a hard mask disposed on top of the mandrel;
forming a layer of insulator material on the substrate and adjacent to the mandrel;
forming a sacrificial stack comprising alternating layers of sacrificial material and dielectric material disposed on the layer of insulator material and adjacent to the mandrel;
patterning and etching the sacrificial stack to form a modified sacrificial stack adjacent to the mandrel and extending 3 nanometers to 15 nanometers from the mandrel;
removing the sacrificial material from the modified sacrificial stack to form growth channels;
epitaxially forming semiconductor in the growth channels; and
etching the semiconductor to align with the end of the growth channels and form a semiconductor stack comprising alternating layers of dielectric material and semiconductor material.
2. The method of claim 1 , further comprising:
removing the mandrel and the hard mask disposed on top of the mandrel;
forming a dummy gate across the semiconductor stack;
forming a first spacer and a second spacer on opposite sides of the dummy gate across the semiconductor stack;
removing the dummy gate; and
removing the dielectric material from the semiconductor stack after removing the dummy gate.
3. The method of claim 1 , wherein the layers of sacrificial material have a thickness of 3 nanometers to 20 nanometers.
4. The method of claim 1 , wherein the layers of dielectric material have a thickness of 5 nanometers to 30 nanometers.
5. The method of claim 1 , wherein the hard mask has a width of 10 nanometers to 100 nanometers.
6. The method of claim 1 , wherein the hard mask comprises hafnium oxide or tungsten.
7. The method of claim 1 , wherein the sacrificial material comprises silicon nitride or silicon dioxide.
8. The method of claim 1 , wherein the dielectric material comprises silicon nitride and the sacrificial material comprises silicon dioxide.
9. The method of claim 1 , wherein the dielectric layer has a thickness of 10 nanometers to 20 nanometers.
10. The method of claim 1 , wherein the semiconductor is a III-V semiconductor.
11. A method for forming a nanowire device, wherein the method comprises:
depositing a hard mask comprising hafnium oxide or tungsten on portions of a silicon substrate having a <110> orientation wherein the hard mask is oriented in the <112> direction;
etching the silicon substrate to form a mandrel having (111) faceted sidewalls and a hard mask disposed on top of the mandrel;
forming a layer of insulator material on the substrate;
forming a sacrificial stack comprising alternating layers of sacrificial material and dielectric material disposed on the layer of insulator material and adjacent to the mandrel;
patterning and etching the sacrificial stack to form a modified sacrificial stack adjacent to the mandrel and extending 3 nanometers to 15 nanometers from the mandrel;
removing the sacrificial material from the modified sacrificial stack to form growth channels;
epitaxially forming III-V semiconductor in the growth channels; and
etching the III-V semiconductor to align with the end of the growth channels and form a semiconductor stack comprising alternating layers of dielectric material and semiconductor material.
12. The method of claim 11 , further comprising:
removing the mandrel and the hard mask disposed on top of the mandrel;
forming a dummy gate across the semiconductor stack;
forming a first spacer and a second spacer on opposite sides of the dummy gate across the semiconductor stack;
removing the dummy gate; and
removing the dielectric material from the semiconductor stack.
13. The method of claim 11 , wherein the layers of sacrificial material have a thickness of 3 nanometers to 20 nanometers and the layers of dielectric material have a thickness of 5 nanometers to 30 nanometers.
14. The method of claim 11 , wherein the hard mask has a width of 10 nanometers to 100 nanometers.
15. The method of claim 11 , wherein the sacrificial material comprises silicon dioxide and the dielectric material comprises silicon nitride.
16. The method of claim 11 , wherein the III-V semiconductor comprises a III-V semiconductor.