Wimpy device by selective laser annealing
A method for co-integrating wimpy and nominal devices includes growing source/drain regions on semiconductor material adjacent to a gate structure to form device structures with a non-electrically active material. Selected device structures are masked with a block mask. Unmasked device structures are selectively annealed to increase electrical activity of the non-electrically active material to adjust a threshold voltage between the selected device structures and the unmasked device structures.
1. A method for co-integrating wimpy and nominal devices, comprising:
growing source/drain regions on semiconductor material adjacent to a gate structure to form device structures with a non-electrically active material; and
selectively annealing unmasked device structures according to a mask over one or more of the device structures to increase electrical activity of the non-electrically active material to adjust a threshold voltage between masked device structures and the unmasked device structures.
2. The method as recited in claim 1 , wherein the non-electrically active material includes Si 3 P 4 .
3. The method as recited in claim 1 , further comprising forming a gate structure including:
forming a dummy gate; and
replacing the dummy gate with a gate conductor after source/drain regions are formed.
4. The method as recited in claim 1 , further comprising forming a gate structure including:
forming a gate conductor before the source/drain regions are formed.
5. The method as recited in claim 1 , wherein selectively annealing the unmasked device structures includes exposing the unmasked device structures to laser light.
6. The method as recited in claim 5 , wherein selectively annealing the masked device structures includes employing a reflective block mask to reflect the laser light.
7. The method as recited in claim 5 , wherein selectively annealing includes annealing to 1200 degrees C. or greater.
8. The method as recited in claim 1 , wherein the masked device structures and the unmasked device structures have a same gate length, same channel doping and same contact pitch.
9. The method as recited in claim 1 , wherein growing source/drain regions includes epitaxially growing silicon in an abundance of phosphine.
10. The method as recited in claim 1 , wherein growing the source/drain regions includes straining the device structures.
11. The method as recited in claim 1 , wherein the threshold voltage is adjusted by decomposition of the non-electrically active material.
12. A method for co-integrating wimpy and nominal devices, comprising:
forming fins on or in a substrate;
forming a gate structure over the fins;
growing source/drain regions on the fins adjacent to the gate structure to form device structures with Si 3 P 4 ; and
selectively annealing unmasked device structures according to a mask over one or more of the device structures to increase electrical activity of the Si 3 P 4 by decomposition to adjust a threshold voltage between masked device structures and the unmasked device structures.
13. The method as recited in claim 12 , wherein forming the gate structure over the fins includes;
forming a dummy gate; and
replacing the dummy gate with a gate conductor after the source/drain regions are formed.
14. The method as recited in claim 12 , wherein forming the gate structure over the fins includes:
forming a gate conductor before the source/drain regions are formed.
15. The method as recited in claim 12 , wherein selectively annealing the unmasked device structures includes exposing the unmasked device structures to laser light.
16. The method as recited in claim 15 , wherein masking the masked device structures with the block mask includes employing a reflective block mask to reflect the laser light.
17. The method as recited in claim 15 , wherein selectively annealing includes annealing to 1200 degrees C. or greater.
18. The method as recited in claim 12 , wherein the masked. device structures and the unmasked device structures have a same gate length, same channel doping and. same contact pitch.
19. The method as recited in claim wherein growing source/drain regions includes epitaxially growing silicon in an abundance of phosphine.
20. The method as recited in claim 12 , wherein growing the source/drain regions includes straining the device structures.