Gate-last semiconductor fabrication with negative-tone resolution enhancement
View Patent ↗A method of fabricating a transistor includes: forming an active device layer on a semiconductor substrate; patterning the active device layer to form fins; forming a first dielectric layer on an upper surface and sidewalls of the fins; forming a second dielectric layer on the first dielectric layer; forming openings through the first and second dielectric layers, exposing the underlying active device layer forming the fins; forming source/drain regions in the active device layer exposed through the respective openings; forming source/drain contacts on an upper surface of the source/drain regions; forming a second opening through the first and second dielectric layers, exposing the underlying active device layer adjacent to the source/drain regions; depositing a third dielectric layer in the second opening, on sidewalls and an upper surface of the fins; and forming a gate stack on the third dielectric layer.
1. A method of fabricating a transistor structure, the method comprising:
forming an active device layer on a semiconductor substrate;
patterning the active device layer to form a plurality of fins;
forming a first dielectric layer on at least a portion of an upper surface and sidewalls of the plurality of fins;
forming a second dielectric layer on at least a portion of an upper surface of the first dielectric layer;
forming a first plurality of openings through the second dielectric layer and the first dielectric layer, exposing the underlying active device layer forming the plurality of fins;
forming a plurality of source/drain regions in the active device layer exposed through the respective first plurality of openings;
forming a plurality of source/drain contacts on an upper surface of each of the plurality of source/drain regions;
forming a second opening through the second dielectric layer and the first dielectric layer, the second opening exposing the underlying active device layer adjacent to the plurality of source/drain regions;
depositing a third dielectric layer in at least a portion of the second opening, including on sidewalls of the second opening and sidewalls and an upper surface of the plurality of fins;
patterning a trench, the trench configured for forming a gate; and
forming the gate on the third dielectric layer using the patterned trench.
2. The method of claim 1 , wherein the gate is formed subsequent to the formation of the source/drain regions, the gate being self-aligned with the plurality of source/drain regions.
3. The method of claim 1 , further comprising forming dielectric spacers on sidewalls of the first plurality of openings prior to forming the plurality of source/drain regions.
4. The method of claim 1 , wherein the third dielectric layer comprises a high dielectric constant material and forms an insulating barrier lining openings between adjacent source/drain contacts.
5. The method of claim 4 , wherein the third dielectric layer comprises at least one of hafnium oxide (HfO), zirconium oxide (ZrO), and aluminum oxide (Al2O3).
6. The method of claim 1 , wherein the third dielectric layer is formed having a cross-sectional thickness of about one to three nanometers (nm).
7. The method of claim 1 , wherein forming the gate comprises:
depositing a conductive material having a prescribed work function associated therewith in the second opening on an upper surface of the third dielectric layer; and
depositing a hard mask layer on an upper surface of the conductive material.
8. The method of claim 1 , wherein the first plurality of openings are oriented in a direction substantially perpendicular to a major axis direction of the plurality of fins.
9. The method of claim 1 , wherein each of at least a subset of the source/drain regions comprises a Group III-V material.
10. The method of claim 9 , wherein the Group III-V material comprises at least one of indium gallium arsenide (InGaAs), gallium arsenide (GaAs) and indium phosphide (InP).
11. The method of claim 1 , wherein forming the source/drain regions comprises doping the source/drain regions during epitaxial deposition by adding at least one impurity to a source gas, a type and amount of the at least one impurity being varied as a function of a desired conductivity type and impurity concentration, respectively, of the source/drain regions.
12. The method of claim 1 , wherein the substrate is a silicon-on-insulator (SOI) substrate comprising a carrier substrate, an insulating layer formed on at least a portion of an upper surface of the carrier substrate, and the active device layer formed on at least a portion of an upper surface of the insulating layer.
13. The method of claim 1 , wherein a vertical height of at least a subset of the plurality of fins above an upper surface of the substrate is about 30 nanometers.
14. The method of claim 1 , wherein the source/drain regions are formed in at least a portion of the first plurality of openings covering the plurality of fins by an epitaxial growth process.
15. The method of claim 14 , wherein the epitaxial growth process comprises at least one of chemical vapor deposition, molecular beam epitaxy, and metal organic chemical vapor deposition epitaxy.