Dummy dielectric fins for finFETs with silicon and silicon germanium channels
A method for forming a semiconductor device includes forming first fins from a first semiconductor material and second fins from a second semiconductor material and encapsulating the first fins and the second fins with a protective dielectric. Semiconductor material between the first fins and the second fins is etched to form trenches. A dielectric fill is employed to fill up the trenches, between the first fins and between the second fins. The first semiconductor material below the first fins and the second semiconductor material below the second fins are oxidized with the first and second fins being protected by the protective dielectric. Fins in an intermediary region between the first fins and the second fins are oxidized to form dummy fins in the intermediary region to maintain a substantially same topology across the device.
1. A semiconductor device, comprising:
first fins formed from a first semiconductor material in a first region;
second fins formed from a second semiconductor material in a second region;
a plurality of dummy fins formed in an intermediary region disposed between a boundary of the first region and a boundary of the second region;
a gate dielectric disposed over the first fins, the second fins and the plurality of dummy fins;
first and second gate conductors disposed over the gate dielectric of the first and second fins, respectively, to form a gate structure over the first and second fins;
dielectric material disposed over the gate dielectric of the plurality of dummy fins; and
a shallow trench isolation region formed beneath the first fins, the second fins and the dummy fins.
2. The semiconductor device as recited in claim 1 , wherein the first fins and the second fins are disposed on dielectric pedestals extending from the shallow trench isolation region.
3. The semiconductor device as recited in claim 1 , wherein the first fins are formed from Si and the second fins are formed from SiGe.
4. The semiconductor device as recited in claim 1 , wherein the gate structure is formed over the first fins and the second fins to connect the first fins and the second fins.
5. The semiconductor device as recited in claim 1 , wherein a given one of the dummy fins includes an oxide material.
6. The semiconductor device as recited in claim 5 , wherein the oxide material includes an oxidized form of the first semiconductor material or an oxidized form of the second semiconductor material.
7. The semiconductor device as recited in claim 1 , wherein the first semiconductor material is different from the second semiconductor material.
8. A semiconductor device, comprising:
first fins formed from silicon in a first region;
second fins formed from a silicon germanium in a second region;
a plurality of dummy fins formed in an intermediary region disposed between a boundary of the first region and a boundary of the second region, wherein a given one of the dummy fins includes an oxidized form of the silicon or an oxidized form of the silicon germanium;
a gate dielectric disposed over the first fins, the second fins and the plurality of dummy fins;
first and second gate conductors disposed over the gate dielectric of the first and second fins, respectively, to form a gate structure over the first and second fins;
dielectric material disposed over the gate dielectric of the plurality of dummy fins; and
a shallow trench isolation region formed beneath the first fins, the second fins and the dummy fins.
9. The semiconductor device as recited in claim 8 , wherein the first fins and the second fins are disposed on dielectric pedestals extending from the shallow trench isolation region.
10. The semiconductor device as recited in claim 8 , wherein the gate structure is formed over the first fins and the second fins to connect the first fins and the second fins.