Uniform shallow trench isolation
A method for forming a field-effect transistor (FET) including forming a plurality of individual fins on a substrate. The method continues with forming a dummy anchor structure, with the dummy anchor located outside the outermost fin. The fins and dummy anchor define a trench, where the trench has a width dimension. The method continues with depositing a shallow trench isolation (STI) material into the trench and between the fins, where the STI material places uniform tension stresses on both sides of the individual fins.
1. A method for forming a field-effect transistor (FET), the method comprising:
forming a plurality of individual fins on a substrate;
forming a dummy anchor structure, wherein the dummy anchor is located outside the outermost fin;
defining a trench between the outermost fin and the dummy anchor, wherein the trench has a width dimension;
depositing a shallow trench isolation (STI) material into the trench and between the fins, wherein the STI material places uniform tension stresses on both sides of the individual fins; and
removing the dummy anchor structure after depositing the STI material.
2. The method of claim 1 , wherein the trench width dimension is equal to a distance between adjacent fins.
3. The method of claim 1 , wherein the trench width dimension is different than a distance between adjacent fins.
4. The method of claim 1 , wherein the dummy anchor structure is comprised of a first liner material and a second liner material, and wherein the first liner material has a width dimension equal to the trench width dimension.
5. The method of claim 1 , wherein the dummy anchor structure is comprised of a first liner material and a second liner material, and wherein the first liner material has a width dimension different than the trench width dimension.
6. The method of claim 1 , further comprising performing an annealing operation to the substrate after depositing a STI material.
7. The method of claim 1 , wherein the plurality of individual fins are formed by a self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) process.
8. The method of claim 1 , further comprising depositing a high-k insulator layer over the substrate after depositing a STI material.
9. The method of claim 1 , further comprising depositing a metal contact layer over the substrate after depositing a STI material.