Vertical transistor with variable gate length

1. A method of forming a vertical transistor, the method comprising:

forming a first pair of fins on a substrate;

forming a second pair of fins on the substrate, wherein the first pair of fins have no fins in common with the second pair of fins;

forming a first trench in the substrate and interposed between each one of the first pair of fins;

forming a second trench in the substrate and interposed between each one of the second pair of fins, wherein the second trench is deeper than the first trench;

forming a first semiconductor structure in the first trench interposed between each one of the first pair of fins, the first semiconductor structure having a first gate region interposed between a first source region and a first drain region, wherein the first source region and the first drain region are separated from each other vertically with the first gate region therebetween; and

forming a second semiconductor structure in the second trench interposed between each one of the second pair of fins, the second semiconductor structure having a first gate region interposed between a second source region and a second drain region, wherein the first gate region and the second gate region have different thicknesses from one another and the second source region and the second drain region are separated from each other vertically with the second gate region therebetween.

2. The method of claim 1 , wherein the first semiconductor structure is formed at the same time as the second semiconductor structure.

3. The method of claim 1 , wherein the first semiconductor structure has a different gate length than the second semiconductor structure.

4. The method of claim 3 , wherein the gate of the first semiconductor structure and the gate of the second semiconductor structure are gate stacks.

5. The method of claim 1 , wherein the first source region, the first drain region, the second source region, and the second drain region are uniform in thickness.

6. The method of claim 5 , wherein a doped first source in the first source region, a doped first drain in the first drain region, a doped second source in the second source region, and a doped second drain in the second drain region are epitaxially grown to a uniform thickness.

7. The method of claim 1 , wherein forming the first and second semiconductor structures comprises:

depositing dielectric material around the first pair of vertical fins and the second pair of vertical fins; and

selectively removing the dielectric material around the second pair of fins.

8. The method of claim 7 , wherein selectively removing the dielectric material comprises removing the dielectric material to form a void around the first pair of fins and the second pair of fins.

9. The method of claim 8 , wherein the void around the second pair of fins is deeper than the void around the second pair of fins.

10. A vertical transistor comprising:

a first pair of fins on a substrate;

a second pair of fins on the substrate, wherein the first pair of fins have no fins in common with the second pair of fins;

a first trench in the substrate and interposed between each one of the first pair of fins;

a second trench in the substrate and interposed between each one of the second pair of fins, wherein the second trench is deeper than the first trench;

a first semiconductor structure in the first trench interposed between one of the first pair of fins, the first semiconductor structure having a first gate region interposed between a first source region and a first drain region, wherein the first source region and the first drain region are separated from each other vertically with the first gate region therebetween; and

a second semiconductor structure in the second trench, which is deeper than the first trench, interposed between each one of the second pair of fins, the second semiconductor structure having a first gate region interposed between a second source region and a second drain region, wherein the first gate region and the second gate region have different thicknesses from one another, wherein the second source region and the second drain region are separated from each other vertically with the second gate region therebetween.

11. The vertical transistor of claim 10 , wherein the first semiconductor structure is formed at the same time as the second semiconductor structure.

12. The vertical transistor of claim 10 , wherein the first semiconductor structure has a different gate length than the second semiconductor structure.

13. The vertical transistor of claim 12 , wherein the gate of the first semiconductor structure and the gate of the second semiconductor structure are gate stacks.

14. The vertical transistor of claim 10 , wherein the first source region, the first drain region, the second source region, and the second drain region are uniform in thickness.

15. The vertical transistor of claim 14 , wherein a doped first source in the first source region, a doped first drain in the first drain region, a doped second source in the second source region, and a doped second drain in the second drain region are epitaxially grown to a uniform thickness.

16. The vertical transistor of claim 10 , wherein the first and second semiconductor structures comprise:

a dielectric material deposited around the first pair of vertical fins and the second pair of vertical fins.

17. The vertical transistor of claim 16 , wherein the dielectric material comprises a void around the first pair of fins and the second pair of fins.

18. The vertical transistor of claim 17 , wherein the void around the second pair of fins is deeper than the void around the first pair of fins.