Laser spike annealing for solid phase epitaxy and low contact resistance in an SRAM with a shared pFET and nFET trench
Embodiments are directed to a method of forming a semiconductor device and resulting structures having a shared SRAM trench and a common contact having a low contact resistance. The method includes forming a first semiconductor fin opposite a surface of a substrate and forming a second semiconductor fin opposite the surface of the substrate and adjacent to the first semiconductor fin. A doped region is formed over portions of each of the first and second semiconductor fins and a dielectric layer is formed over the doped regions. A shared trench is formed in the dielectric layer exposing portions of the doped regions. The exposed doped regions are then amorphized and recrystallized.
1. A semiconductor device comprising:
a first semiconductor fin formed opposite a surface of a substrate;
a second semiconductor fin formed opposite the surface of the substrate and adjacent to the first semiconductor fin;
a first doped region formed over portions of the first semiconductor fin;
a second doped region formed over portions of the second semiconductor fin; and
a shared conductive contact comprising a contact resistivity of less than about 2.5×10 −9 Ω·cm −2 formed over the first and second doped regions.
2. The semiconductor device of claim 1 , wherein the first and second doped regions each comprise a crystalline structure.
3. The semiconductor device of claim 1 , wherein the first and second doped regions each comprise a polycrystalline structure.
4. The semiconductor device of claim 1 , wherein the first and second doped regions each comprises a Ge or Si dopant concentration of at least 1×10 21 cm −3 .
5. The semiconductor device of claim 1 , wherein the first doped region comprises p type dopants.
6. The semiconductor device of claim 5 , wherein the p-type dopants are selected from the group consisting of B, BF 2 , Al, and Ga.
7. The semiconductor device of claim 1 , wherein the second doped region comprises n type dopants.
8. The semiconductor device of claim 7 , wherein the n-type dopants are selected from the group consisting of As, P, and Sb.
9. The semiconductor device of claim 1 , wherein the first semiconductor fin and the second semiconductor fin are formed in a shared trench in a dielectric layer.
10. The semiconductor device of claim 1 , wherein the first doped region comprises a first epitaxy region formed over the first semiconductor fin, wherein the first epitaxy region is doped with p-type dopants.
11. The semiconductor device of claim 1 , wherein the second doped region comprises a second epitaxy region formed over the second semiconductor fin, wherein the second epitaxy region is doped with n-type dopants.
12. A semiconductor device comprising:
a first semiconductor fin formed opposite a surface of a substrate;
a second semiconductor fin formed opposite the surface of the substrate and adjacent to the first semiconductor fin;
a first doped region comprising n type dopants formed over portions of the first semiconductor fin;
a second doped region comprising p type dopants formed over portions of the second semiconductor fin; and
a shared conductive contact comprising a contact resistivity of less than about 2.5×10 −9 Ω·cm −2 formed over the first and second doped regions.
13. The semiconductor device of claim 12 , wherein the first and second doped regions each comprise a crystalline structure.
14. The semiconductor device of claim 12 , wherein the first and second doped regions each comprise a polycrystalline structure.
15. The semiconductor device of claim 12 , wherein the first and second doped regions each comprises a Ge or Si dopant concentration of at least 1×10 21 cm −3 .
16. The semiconductor device of claim 12 , wherein the p-type dopants are selected from the group consisting of B, BF 2 , Al, and Ga.
17. The semiconductor device of claim 12 , wherein the n-type dopants are selected from the group consisting of As, P, and Sb.
18. The semiconductor device of claim 12 , wherein the first semiconductor fin and the second semiconductor fin are formed in a shared trench in a dielectric layer.
19. The semiconductor device of claim 12 , wherein the first doped region comprises a first epitaxy region formed over the first semiconductor fin, wherein the first epitaxy region is doped with n-type dopants.
20. The semiconductor device of claim 12 , wherein the second doped region comprises a second epitaxy region formed over the second semiconductor fin, wherein the second epitaxy region is doped with p-type dopants.