Method and structure to enable dual channel fin critical dimension control

1. A method for manufacturing a semiconductor device, comprising:

forming a first semiconductor layer on a substrate having a {100} crystallographic surface orientation, wherein the first semiconductor layer comprises a first semiconductor material;

forming a second semiconductor layer on the substrate, wherein the second semiconductor layer comprises a second semiconductor material different from the first semiconductor material;

patterning the first semiconductor layer and the second semiconductor layer into a first plurality of fins and a second plurality of fins, respectively, wherein the first and second plurality of fins extend vertically with respect to the substrate;

wherein the patterning comprises simultaneously etching the first semiconductor layer and the second semiconductor layer, wherein the second semiconductor layer is etched at a faster rate than the first semiconductor layer so that a critical dimension of each of the second plurality of fins is less than a critical dimension of each of the first plurality of fins;

covering the first plurality of fins and a portion of the substrate corresponding to the first plurality of fins; and

epitaxially growing semiconductor layers on exposed portions of the second plurality of fins and on exposed portions of the substrate, wherein the epitaxially grown semiconductor layers on the exposed portions of the second plurality of fins increase the critical dimension of each of the second plurality of fins so that the critical dimension of each of the second plurality of fins is the same or substantially the same as the critical dimension of each of the first plurality of fins.

2. The method according to claim 1 , wherein the patterning of the first semiconductor layer and the second semiconductor layer into the first and the second plurality of fins comprises:

forming a hardmask on portions of the first and second semiconductor layers to be patterned into the first and second plurality of fins; and

etching exposed portions the first and second semiconductor layers.

3. The method according to claim 2 , wherein the hardmask remains on a top surface of the each of the second plurality of fins during the epitaxially growing and prevents epitaxial growth on the top surface of the each of the second plurality of fins.

4. The method according to claim 1 , wherein the epitaxially grown semiconductor layers are conformally grown on the exposed portions of the second plurality of fins and on exposed portions of the substrate.

5. The method according to claim 1 , wherein the covering of the first plurality of fins and the portion of the substrate corresponding to the first plurality of fins comprises depositing an organic planarization layer on the first plurality of fins and on the portion of the substrate corresponding to the first plurality of fins.

6. The method according to claim 5 , further comprising removing the organic planarization layer after epitaxially growing the semiconductor layers on the exposed portions of the second plurality of fins and on the exposed portions of the substrate.

7. The method according to claim 1 , wherein forming the first and second semiconductor layers on the substrate comprises epitaxially growing the first and second semiconductor layers on the substrate.

8. The method according to claim 1 , wherein the first semiconductor material comprises silicon.

9. The method according to claim 1 , wherein the second semiconductor material comprises silicon germanium.

10. The method according to claim 1 , wherein:

the covering of the first plurality of fins and the portion of the substrate corresponding to the first plurality of fins comprises depositing a blocking material on the first plurality of fins and on the portion of the substrate corresponding to the first plurality of fins; and

the method further comprises removing the blocking material after epitaxially growing the semiconductor layers on the exposed portions of the second plurality of fins and on the exposed portions of the substrate.

11. The method according to claim 10 , further comprising forming a gate structure on a portion of each of the first plurality of fins and the second plurality of fins.

12. The method according to claim 11 , further comprising:

depositing a second blocking material to cover exposed portions of the first plurality of fins adjacent the gate structure;

conformally increasing sizes of exposed portions of the second plurality of fins adjacent the gate structure by epitaxial growth; and

removing the second blocking material.

13. The method according to claim 12 , further comprising:

depositing a third blocking material to cover the exposed portions of the second plurality of fins adjacent the gate structure;

conformally increasing sizes of the exposed portions of the first plurality of fins adjacent the gate structure by epitaxial growth; and

removing the third blocking material.

14. The method according to claim 13 , further comprising forming a contact region between each of the first and second plurality of fins adjacent the gate structure that were conformally increased in size.

15. A method for manufacturing a semiconductor device, comprising:

forming a first semiconductor layer on a substrate having a {100} crystallographic surface orientation, wherein the first semiconductor layer comprises a first semiconductor material;

forming a second semiconductor layer on the substrate, wherein the second semiconductor layer comprises a second semiconductor material different from the first semiconductor material;

patterning the first semiconductor layer and the second semiconductor layer into a first plurality of fins and a second plurality of fins, respectively, wherein the first and second plurality of fins extend vertically with respect to the substrate;

wherein the patterning comprises simultaneously etching the first semiconductor layer and the second semiconductor layer, wherein the second semiconductor layer is etched at a faster rate than the first semiconductor layer so that a critical dimension of each of the second plurality of fins is less than a critical dimension of each of the first plurality of fins;

depositing a blocking material on the first plurality of fins and on a portion of the substrate corresponding to the first plurality of fins to cover the first plurality of fins and the portion of the substrate corresponding to the first plurality of fins;

epitaxially growing semiconductor layers on exposed portions of the second plurality of fins and on exposed portions of the substrate, wherein the epitaxially grown semiconductor layers on the exposed portions of the second plurality of fins increase the critical dimension of each of the second plurality of fins to be the same or substantially the same as the critical dimension of each of the first plurality of fins; and

removing the blocking material.

16. The method according to claim 15 , wherein the epitaxially grown semiconductor layers are conformally grown on the exposed portions of the second plurality of fins and on exposed portions of the substrate.

17. The method according to claim 1 , wherein the increase in the critical dimension of each of the second plurality of fins is limited to a lateral direction by a hardmask positioned on a top surface of the each of the second plurality of fins.

18. The method according to claim 15 , wherein the increase in the critical dimension of each of the second plurality of fins is limited to a lateral direction by a hardmask positioned on a top surface of the each of the second plurality of fins.