Formation of full metal gate to suppress interficial layer growth

1. A method of fabricating a semiconductor device having an n-channel field effect transistor (nFET) bottom junction and a p-channel field effect transistor (pFET) bottom junction, the method comprising:

forming first and second fin formations in the nFET and pFET bottom junctions, respectively;

depositing an nFET metal gate layer for oxygen absorption directly onto a high-k dielectric layer provided about the first fin formation in the nFET bottom junction;

depositing the nFET metal gate layer directly onto a pFET metal gate layer provided about the second fin formation in the pFET bottom junction;

terminating the nFET metal gate layer and the high-k dielectric layer along sidewalls of the first fin formation in the nFET bottom junction;

terminating the nFET metal gate layer, the pFET metal gate layer and the high-k dielectric layer along sidewalls of the second fin formation in the pFET bottom junction; and

sequentially depositing encapsulation and oxide layers such that upper portions of the first and second fin formations and corresponding sections of the encapsulation layer protrude from the oxide layer in the nFET and pFET regions;

depositing nitride about the upper portions of the first and second fin formations and corresponding sections of the encapsulation layer in the nFET and pFET regions;

etching through the oxide layer, the encapsulation layer, the nFET metal gate layer and the high-k dielectric layer in the nFET region to form an isolated gate element in the nFET region; and

etching through the oxide layer, the encapsulation layer, the nFET metal gate layer, the pFET metal gate layer and the high-k dielectric layer to form an isolated gate element in the pFET region.

2. The method according to claim 1 , wherein the nFET metal gate layer comprises a single layer or multiple layers.

3. The method according to claim 1 , wherein the nFET metal gate layer comprises at least one or more of titanium nitride (TiN), titanium aluminum carbide (TiAlC), tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), aluminum (Al), titanium aluminum (TiAl), titanium (Ti), other similar materials or combinations thereof or any materials containing metallic Al or metallic Ti and metallic nitrides or metallic carbides.

4. The method according to claim 1 , wherein the pFET metal gate layer comprises a single layer or multiple layers.

5. The method according to claim 1 , wherein the pFET metal gate layer comprises at least one or more of metal nitride or metal carbide including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium carbide (TiC), tantalum carbide (TaC), or pure pFET work function metals including tungsten (W), Nickle (Ni), Platinum (Pt) or Cobalt or combinations thereof.

6. The method according to claim 1 , wherein:

a surface of the nFET metal gate layer directly abuts a complementary surface of the high-k dielectric layer in the nFET bottom junction, and

a surface of the nFET metal gate layer directly abuts a complementary surface of the pFET metal gate layer in the pFET bottom junction.

7. The method according to claim 1 , wherein:

the first and second fin formations respectively comprise a semiconductor section and a hard mask section above an uppermost surface of the semiconductor section,

the sidewalls of the first and second fin formations respectively extending along the respective semiconductor sections, and

the terminating comprising:

a deposition of a planarization layer in the nFET and pFET bottom junctions; and

a recession of the nFET metal gate layer and the high-k dielectric layer in the nFET bottom junction and the nFET metal gate layer, the pFET metal gate layer and the high-k dielectric layer in the pFET bottom junction to an uppermost surface of the planarization layer.