Vertical transistor with uniform bottom spacer formed by selective oxidation

1. A method of forming a vertical transistor, the method comprising:

forming at least one fin on stacked layers comprising a substrate, a doped silicon layer, and an intrinsic layer interposed between the at least one fin and the substrate;

forming a spacer hardmask over the at least one fin; and

forming a bottom spacer, wherein forming the bottom spacer comprises selective oxidation of the intrinsic layer;

opening a plurality of gate trenches surrounding the two or more fins; and

forming a metal gate stack in each of the plurality of gate trenches

wherein forming the metal gate stack comprises:

recessing a top portion of the metal gate stack;

forming a top spacer; and

forming a top source or drain (S/D) region on the top spacer.

2. The method of claim 1 , further comprising:

forming a shallow trench isolation (STI) interposed between two or more fins.

3. The method of claim 2 , comprising two or more fins comprising a fin pitch of no more than 40 nm.

4. The method of claim 2 , wherein forming the plurality of gate trenches comprises etching the spacer hardmask at a base of the plurality of gate trenches to expose the doped silicon layer.

5. The method of claim 1 , wherein forming the spacer hardmask over the at least one fin comprises conformal deposition of amorphous siliconborocarbonitride (SiBCN).

6. The method of claim 1 , wherein the spacer hardmask has a material thickness of 8 nm.

7. The method of claim 1 , wherein the S/D region formed on the metal gate stacks comprise a merged S/D region.

8. The method of claim 1 , wherein the S/D region formed on the metal gate stacks comprise unmerged source and drain regions.