Interconnect structure and fabrication thereof
Interconnect structures and processes generally include creating point defects in exposed surfaces of the dielectric layer to create a point defect region at a relatively shallow depth, wherein the point defect region is a fraction of the dielectric layer and is created with exposure to silicon, carbon, nitrogen, oxygen, or mixtures thereof such that the point defect region contains Si, C, N O, or mixtures containing at least one of the foregoing. A seed layer can be deposited and includes at least one alloying element that is effective to form an in situ self-aligned liner layer with the Si, C, N O, or mixtures containing at least one of the foregoing within the point defect region, which is formed at a depth of less than 10 nanometers. The in situ liner layer within the dielectric layer maximizes the volume fraction of the conductor of the interconnect structure.
1. A method for forming an interconnect structure in an integrated circuit comprising:
providing a patterned substrate comprising an opening in a dielectric layer, wherein the opening includes sidewalls formed of the dielectric layer and a bottom surface comprising a source region or a drain region or a metal gate or the dielectric layer;
creating point defects in exposed surfaces of the dielectric layer to create a point defect region, wherein the point defect region is a fraction of the dielectric layer and is created with exposure to silicon, carbon, nitrogen, oxygen, or mixtures thereof such that the point defect region contains Si, C, N O, or mixtures containing at least one of the foregoing;
depositing a seed layer onto the point defect region, wherein the seed layer comprises at least one alloying element;
depositing a conductor layer onto the seed layer; and
annealing the patterned substrate to form an in situ liner layer in the point defect region of the dielectric layer from the at least one alloying element and Si, C, N O, or mixtures containing at least one of the foregoing.
2. The method of claim 1 , further comprising depositing a conformal liner layer onto the dielectric layer at a thickness of less than 40 Angstroms, wherein depositing the conformal layer is after creating the point defects in the exposed surfaces of the dielectric layer.
3. The method of claim 2 , wherein the conformal liner layer deposited onto the dielectric layer is formed of a metal comprising tantalum, ruthenium, rhodium, iridium, cobalt, or mixtures comprising at least one of the foregoing.
4. The method of claim 1 , wherein the at least one alloying element in the seed layer comprises aluminum, manganese, nickel or mixtures thereof.
5. The method of claim 1 , wherein creating the point defects comprises penetrating the exposed surfaces of the dielectric layer with particles to a depth of less than 10 nanometers.
6. The method of claim 1 , wherein creating the point defects comprises penetrating the exposed surfaces of the dielectric layer with particles to a depth of greater than 0.5 nanometers to less than 3 nanometers.
7. The method of claim 1 , wherein the creating the point defects comprises ion implantation at energies of 10 keV to 200 keV, plasma bombardment at energies of 0.1 keV to 2 keV, gas cluster ion bombardment at energies of 10 keV to 30 keV and accelerated neutral atom beam at energies of 10 eV to 200 eV.
8. The method of claim 1 , wherein creating the point defects comprises exposing the dielectric layer to particles in an amount and at an energy effective to form pores and/or cracks in the dielectric layer.
9. The method of claim 3 , wherein exposing the dielectric layer to particles comprises an accelerated neutral atom beam at energies of 10 eV to 200 eV, wherein the particles are electrically neutral.
10. The method of claim 1 , further comprising chemical mechanically polishing after the annealing to remove an overburden of the conductor layer, the in situ liner layer, and the seed layer from an uppermost surface of the dielectric layer.
11. The method of claim 1 , further comprising chemical mechanically polishing prior to the annealing to remove an overburden of the conductor layer and the seed layer from an uppermost surface of the dielectric layer, wherein the annealing further forms a liner layer on a top surface of the conductor layer.
12. The method of claim 1 , further comprising chemical mechanically polishing prior to the annealing to remove an overburden of the conductor layer and the seed layer from an uppermost surface of the dielectric layer, wherein the annealing further forms a second liner layer from the at least one alloying element on a top surface of the conductor layer.