Asymmetric junction engineering for narrow band gap MOSFET
A method for forming a semiconductor device. It includes forming fin structures on a substrate, where the fin structure defines source and drain regions. It also includes forming a gate stack in contact with the fin structure, depositing an insulator on the substrate, and applying an etching process to remove portions of the insulator to form a trench to the source region. It also includes implanting a damaged epitaxial material into the trench and to the source regions, and applying a second etching process to remove portions of the insulator to form a trench in the insulator to the drain regions. Finally, the method includes growing an epitaxial junction material over the source and drain regions, and depositing a metal over the substrate.
1. A semiconductor device comprising:
a fin structures comprising a first material formed on a substrate;
gate, source, and drain regions comprising a second material formed on the substrate;
a contact insulator layer deposited over the substrate;
wherein a first etching process applied to the substrate removes a first portion of the contact insulator to create a first trench in the contact insulator layer that extends to the source region;
a damaged epitaxial material that is deposited into the trench that extends to the source region;
an epitaxial junction material that is grown over the source and drain regions; and
a metalizing contact material that is deposited over the substrate.
2. The device of claim 1 , wherein the contact insulator layer is comprised of indium aluminum arsenide (InAlAs) or indium phosphide (InP).
3. The device of claim 1 , wherein the fin structure is comprised of indium gallium arsenide (InGaAs) or silicon germanium (SiGe).
4. The device of claim 1 , wherein the damaged epitaxial material is comprised of silicon (Si), argon (Ar), xenon (Xe), or germanium (Ge).
5. The device of claim 1 , wherein the fin structure is instead a nanowire, a nanosheet, or a planar device.
6. The device of claim 1 , wherein the fin structure is formed by Aspect Ratio Trapping (ART) or Strain Relaxed Buffer (SRB) processes.
7. The device of claim 1 , wherein the epitaxial junction material is grown, doped, and diffused with n+ material for NFET devices and p+ material for PFET devices.
8. The device of claim 1 , wherein the epitaxial junction material possesses higher leakage rates due to defects, physical damage, or doping introduced into the material, and is has a growth temperature too low to anneal all damage.
9. The device of claim 1 , further comprising a planarized contact insulator layer.
10. The device of claim 1 , wherein a second trench extends to the drain region and damaged epitaxial material is injected into the trench.
11. The device of claim 2 , wherein a second etching process applied to the substrate removes a second portion of the contact insulator layer to create the second trench in the contact insulator layer that extends to the drain region.
12. The device of claim 11 , wherein the trench is adjacent to the fin structure.
13. The device of claim 12 , wherein the epitaxial junction contacts both the first and second trenches.
14. The device of claim 13 , wherein the epitaxial junction comprise indium gallium arsenide (InGaAs).
15. The device of claim 11 , wherein the damaged epitaxial material directs parasitic current flow to the source.
16. The device of claim 15 , wherein the parasitic current flow is diverted from the drain.
17. The device of claim 16 , wherein directing the parasitic current flow to the source reduces overall parasitic current effects in the device.
18. The device of claim 11 , wherein the damaged epitaxial material directs parasitic current flow to the drain.
19. The device of claim 15 , wherein the parasitic current flow is diverted from the source.
20. The device of claim 16 , wherein directing the parasitic current flow to the drain reduces overall parasitic current effects in the device.