IP Library Granted Patent US 10,256,159
Granted Patent B2
US 10,256,159 · App. 15/412,499 · Granted Apr 9, 2019

Formation of common interfacial layer on Si/SiGe dual channel complementary metal oxide semiconductor device

Inventors: Ruqiang Bao (Wappingers Falls, NY); Hemanth Jagannathan (Niskayuna, NY); ChoongHyun Lee (Rensselaer, NY); Shogo Mochizuki (Clifton Park, NY)
Assignee: International Business Machines Corporation
H01L21/823857H01L21/31122H01L27/092
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Quick Facts
Patent No.
US 10,256,159
App. No.
15/412,499
Granted
Apr 9, 2019
Kind
B2
Abstract

A method is presented for forming a semiconductor structure. The method includes forming a silicon (Si) channel for a first device, forming a first interfacial layer over the Si channel, forming a silicon-germanium (SiGe) channel for a second device, forming a second interfacial layer over the SiGe channel, and selectively removing germanium oxide (GeO X ) from the second interfacial layer by applying a combination of hydrogen (H 2 ) and hydrogen chloride (HCl). The second interfacial is silicon germanium oxide (SiGeO X ) and removal of the GeO X results in formation of a pure silicon dioxide (SiO 2 ) layer.

Claims (16)

1. A method for forming a semiconductor structure, the method comprising:

forming a first channel for a first device;

forming a first interfacial layer in direct contact with the first channel;

forming a second channel for a second device;

forming a second interfacial layer in direct contact with the second channel, where the first interfacial layer is constructed from a different material than the second interfacial layer; and

selectively removing germanium oxide (GeO X ) from the second interfacial layer by applying a combination of gases to convert the first interfacial layer to have a same chemical compound as the second interfacial layer; and

depositing a high-k metal gate in direct contact with the converted first interfacial layer.

2. The method of claim 1 , wherein the first device is an n-type field effect transistor (nFET).

3. The method of claim 1 , wherein the second device is a p-type field effect transistor (pFET).

4. The method of claim 1 , wherein the first channel is silicon (Si), the second channel is silicon germanium (SiGe), and the second interfacial is silicon germanium oxide (SiGeO X ).

5. The method of claim 1 , wherein removal of the GeO X results in formation of a pure silicon dioxide (SiO 2 ) layer.

6. The method of claim 1 , wherein the converted first interfacial layer is formed between spacers.

7. The method of claim 6 , wherein the combination of gases are applied to sidewalls of the spacers before the converted first interfacial layer is formed.

8. The method of claim 1 , wherein removal of the GeO X prevents breaking of Si—O bonds in the second interfacial layer.

9. The method of claim 1 , wherein removal of the GeO X results in decreased interface trap density in the second interfacial and the second channel.

10. The method of claim 1 , wherein the gases are a combination of hydrogen (H 2 ) and hydrogen chloride (HCl).

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052644/0868 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2017
From: BAO, RUQIANG; JAGANNATHAN, HEMANTH; LEE, CHOONGHYUN; MOCHIZUKI, SHOGO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 041047/0680 →
Continuity (1)
Related Publication 20180211885A1 · Jul 26, 2018