IP Library Granted Patent US 10,164,103
Granted Patent B2
US 10,164,103 · App. 15/294,986 · Granted Dec 25, 2018

Forming strained channel with germanium condensation

Inventors: Kangguo Cheng (Schenectady, NY); Shogo Mochizuki (Schenectady, NY); Jie Yang (Clifton Park, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L29/785H01L21/26513H01L29/0847H01L29/165H01L29/6656H01L29/66545H01L29/66795H01L29/7848
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Quick Facts
Patent No.
US 10,164,103
App. No.
15/294,986
Granted
Dec 25, 2018
Kind
B2
Abstract

A method for forming a semiconductor device includes forming a strained fin on a substrate, a sacrificial gate on a channel region of the fin, a first spacer adjacent to a sidewall of the fin, and a second spacer adjacent to the first spacer. A source/drain region is grown on an exposed portion of the fin. Atoms are driven from the source/drain region into the fin and form an oxide layer on the source/drain region. The second spacer and the oxide layer are removed. An insulator layer is formed over the source/drain region, and the sacrificial gate is removed to expose the channel region of the fin. A gate stack is formed over the channel region of the fin.

Claims (46)

1. A method for forming a semiconductor device, the method comprising:

forming a strained fin on a substrate;

forming a sacrificial gate on a channel region of the fin;

forming a first spacer adjacent to a sidewall of the fin;

forming a second spacer adjacent to the first spacer;

growing a source/drain region on an exposed portion of the fin;

annealing to drive atoms from the source/drain region into the fin and form an oxide layer on the source/drain region;

removing the second spacer and the oxide layer;

forming an insulator layer over the source/drain region;

removing the sacrificial gate to expose the channel region of the fin; and

forming a gate stack over the channel region of the fin.

2. The method of claim 1 , wherein the substrate includes silicon.

3. The method of claim 1 , wherein the strained fin includes SiGe.

4. The method of claim 1 , wherein the source/drain region includes Ge.

5. The method of claim 1 , wherein the atoms are Ge atoms.

6. The method of claim 1 , wherein the annealing increases a concentration of Ge atoms in the fin.

7. The method of claim 1 , wherein the first spacer includes a nitride material and the second spacer includes an oxide material.

8. The method of claim 1 , wherein the strained fin is compressively strained.

9. The method of claim 1 , further comprising:

forming a source/drain extension region by implanting dopants in the after removing the second spacer;

removing portions of the insulator layer to expose the source/drain region; and

forming a conductive contact over the source/drain region.

10. A method for forming a semiconductor device, the method comprising:

forming a strained semiconductor layer on a substrate;

removing portions of the strained semiconductor layer to form a fin on the substrate;

depositing an insulator layer on the substrate;

forming a sacrificial gate on a channel region of the fin;

forming a first spacer adjacent to a sidewall of the fin;

forming a second spacer adjacent to the first spacer;

growing a source/drain region on an exposed portion of the fin;

annealing to drive atoms from the source/drain region into the fin and form an oxide layer on the source/drain region;

removing the second spacer and the oxide layer;

forming an insulator layer over the source/drain region;

removing the sacrificial gate to expose the channel region of the fin; and

forming a gate stack over the channel region of the fin.

11. The method of claim 10 , wherein the substrate includes silicon.

12. The method of claim 10 , wherein the strained semiconductor layer includes SiGe.

13. The method of claim 10 , wherein the source/drain region includes Ge.

14. The method of claim 10 , wherein the atoms are Ge atoms.

15. The method of claim 10 , wherein the annealing increases a concentration of Ge atoms in the fin.

16. The method of claim 10 , wherein the first spacer includes a nitride material and the second spacer includes an oxide material.

17. The method of claim 10 , wherein the strained semiconductor layer is compressively strained.

18. The method of claim 10 , further comprising:

forming a source/drain extension region by implanting dopants in the after removing the second spacer;

removing portions of the insulator layer to expose the source/drain region; and

forming a conductive contact over the source/drain region.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052644/0868 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2016
From: CHENG, KANGGUO; MOCHIZUKI, SHOGO; YANG, JIE
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 040033/0302 →
Continuity (1)
Related Publication 20180108769A1 · Apr 19, 2018