Forming a combination of long channel devices and vertical transport fin field effect transistors on the same substrate
A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, including, forming a recessed region in a substrate and a fin region adjacent to the recessed region, forming one or more vertical fins on the fin region, forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins, forming two or more long-channel source/drain plugs on the long-channel pillar, forming a bottom source/drain plug in the fin region, where the bottom source/drain plug is below the one or more vertical fins, forming a gate structure on the long-channel pillar and a gate structure on the one or more vertical fins, and forming a top source/drain on the top surface of the one or more vertical fins.
1. A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor, comprising:
forming a recessed region in a substrate and a fin region adjacent to the recessed region;
forming one or more vertical fins on a vertical fin block in the fin region; and
forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins.
2. The method of claim 1 , wherein the recessed region is formed to a depth greater than the height of the one or more vertical fins.
3. The method of claim 2 , wherein the depth is in a range of about 20 nm to about 100 nm.
4. The method of claim 1 , wherein the top surface of the long-channel pillar is below the top surface of the vertical fin block.
5. The method of claim 1 , further comprising forming a pillar gate structure on the long-channel pillar; and
forming a fin gate structure on the one or more vertical fins.
6. The method of claim 1 , wherein the fin region has a width in a range of about 20 nm to about 800 nm and a length in a range of about 20 nm to about 200 nm.
7. The method of claim 1 , further comprising forming a dielectric fill layer that covers the long-channel pillar but not the one or more vertical fins.
8. The method of claim 7 , further comprising forming an organic planarization layer (OPL) on the fill layer, and forming access passages in the OPL and fill layer.
9. The method of claim 8 , further comprising forming source/drain troughs in the long-channel pillar and vertical fin block;
forming bottom source/drain plugs in the source/drain troughs in the vertical fin block; and
forming long-channel source/drain plugs in the source/drain troughs in the long-channel pillar.
10. A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, comprising:
forming a recessed region in a substrate and a fin region adjacent to the recessed region;
forming one or more vertical fins on a vertical fin block in the fin region, where the one or more vertical fins extend away from the substrate;
forming a long-channel pillar from the substrate in the recessed region, wherein the top surface of the long-channel pillar is below the bottom of the one or more vertical fins;
forming a dielectric fill layer that covers the long-channel pillar but not the one or more vertical fins; and
forming an organic planarization layer (OPL) on the fill layer and the one or more vertical fins.
11. The method of claim 10 , wherein the long-channel pillar has a length in the range of about 100 nm to about 600 nm.
12. The method of claim 11 , wherein the long-channel pillar has a height in the range of about 5 nm to about 50 nm.
13. The method of claim 12 , further comprising forming bottom source/drain plugs in the vertical fin block; and
forming long-channel source/drain plugs in the long-channel pillar.
14. The method of claim 13 , wherein the one or more vertical fins have a height in the range of about 30 nm to about 90 nm.
15. A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, comprising:
forming a recessed region in a substrate and a fin region adjacent to the recessed region;
forming one or more vertical fins on a vertical fin block in the fin region, where the one or more vertical fins extend away from the substrate;
forming a long-channel pillar from the substrate in the recessed region, wherein the top surface of the long-channel pillar is below the bottom of the one or more vertical fins;
forming a dielectric fill layer that covers the long-channel pillar but not the one or more vertical fins;
forming an organic planarization layer (OPL) on the fill layer and the one or more vertical fins;
forming a pillar gate structure on the long-channel pillar;
forming a fin gate structure on the one or more vertical fins; and
forming a top source/drain on the top surface of the one or more vertical fins, where the top source/drain is in the fin region.
16. The method of claim 15 , wherein the pillar gate structure on the long-channel pillar has an inverted “T” shape directly above a central section of the long-channel pillar.
17. The method of claim 16 , wherein the fin gate structure on the one or more vertical fins includes a gate dielectric layer and a gate fill layer.
18. The method of claim 16 , wherein the top source/drain is silicon-germanium (SiGe) with a germanium concentration in the range of about 40 at. % Ge to about 80 at. % Ge.
19. The method of claim 16 , wherein the long-channel pillar has a height in the range of about 5 nm to about 50 nm.
20. The method of claim 16 , further comprising forming separate electrical contacts to each of the top source/drain, pillar gate structure, and fin gate structure.