Forming a combination of long channel devices and vertical transport fin field effect transistors on the same substrate
A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, including, forming a recessed region in a substrate and a fin region adjacent to the recessed region, forming one or more vertical fins on the fin region, forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins, forming two or more long-channel source/drain plugs on the long-channel pillar, forming a bottom source/drain plug in the fin region, where the bottom source/drain plug is below the one or more vertical fins, forming a gate structure on the long-channel pillar and a gate structure on the one or more vertical fins, and forming a top source/drain on the top surface of the one or more vertical fins.
1. A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, comprising:
forming a recessed region in a substrate and a fin region adjacent to the recessed region;
forming one or more vertical fins on the fin region, where the one or more vertical fins extend away from the substrate;
forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins;
forming two or more long-channel source/drain plugs on the long-channel pillar;
forming a bottom source/drain plug in the fin region, where the bottom source/drain plug is below the one or more vertical fins;
forming a gate structure on the long-channel pillar and a gate structure on the one or more vertical fins; and
forming a top source/drain on the top surface of the one or more vertical fins, where the top source/drain is in the fin region.
2. The method of claim 1 , wherein the one or more vertical fins are formed by a sidewall image transfer (SIT) process, a self-aligned double patterning (SADP) process, or a self-aligned quadruple patterning (SAQP) process.
3. The method of claim 1 , wherein the gate structure on the long-channel pillar has an inverted “T” shape directly above a central section of the long-channel pillar.
4. The method of claim 1 , wherein the top surface of the long-channel pillar is below the bottom of the one or more vertical fins.
5. The method of claim 1 , further comprising forming a segregating trench between the long-channel pillar and fin region, and filling the segregating trench with an insulating dielectric material to provide an isolation region.
6. The method of claim 1 , wherein the bottom source/drain plug is epitaxially grown on the fin region adjacent to the one or more vertical fins, and the two or more long-channel source/drain plugs are epitaxially grown on the long-channel pillar.
7. The method of claim 6 , further comprising heat treating the bottom source/drain plug and the two or more long-channel source/drain plugs to form a bottom source/drain and two or more long-channel source/drains.
8. The method of claim 7 , further comprising forming electrical contacts to the long-channel source/drain, bottom source/drain, top source/drain, long-channel gate structure, and vertical fin gate structure.
9. The method of claim 7 , wherein the top source/drain is silicon-germanium (SiGe) with a germanium concentration in the range of about 40 at. % Ge to about 80 at. % Ge, and the bottom source/drain and top source/drain is doped with boron, gallium, or indium.
10. A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, comprising:
forming a recessed region in a substrate and a fin region adjacent to the recessed region;
forming one or more vertical fins on the fin region, where the one or more vertical fins extend away from the substrate;
forming a long-channel pillar from the substrate in the recessed region, wherein the top surface of the long-channel pillar is below the bottom of the one or more vertical fins;
forming a gate structure on the long-channel pillar, wherein the gate structure on the long-channel pillar has an inverted “T” shape directly above a central section of the long-channel pillar; and
forming a gate structure on the one or more vertical fins.
11. The method of claim 10 , wherein the gate structure on the long-channel pillar includes a gate cavity and a gate opening, where the gate cavity is wider than the gate opening to form the inverted “T” shape.
12. The method of claim 10 , wherein the substrate can be n-doped or p-doped.
13. The method of claim 10 , wherein the long-channel pillar has a height in the range of about 5 nm to about 50 nm, and the top surface of the long-channel pillar is below the bottom of the vertical fins.
14. The method of claim 10 , wherein the one or more vertical fins have a height in the range of about 30 nm to about 90 nm.