Semiconductor device and method for fabricating the same
A method for fabricating a semiconductor device includes the steps of providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first gate structure on the substrate and a first epitaxial layer adjacent to the first gate structure, in which a top surface of the first epitaxial layer includes a first V-shape. The LV device includes a second gate structure on the substrate and a second epitaxial layer adjacent to the second gate structure, in which a top surface of the second epitaxial layer includes a first planar surface.
1 . A method for fabricating a semiconductor device, comprising:
providing a substrate having a high-voltage (HV) region, a low-voltage (LV) region, and a dummy region between the HV region and the LV region;
forming a HV device on the HV region, wherein the HV device comprises:
a first gate structure on the substrate; and
a first epitaxial layer adjacent to the first gate structure, wherein a top surface of the first epitaxial layer comprises a first V-shape;
forming a LV device on the LV region, wherein the LV device comprises:
a second gate structure on the substrate; and
a second epitaxial layer adjacent to the second gate structure, wherein a top surface of the second epitaxial layer comprises a first planar surface; and
forming a dummy device on the dummy region, wherein the dummy region comprises a ring shape around the LV region.
2 . The method of claim 1 , wherein the first epitaxial layer comprises:
a first inclined sidewall;
a second inclined sidewall; and
a second planar surface connecting the first inclined sidewall and the second inclined sidewall.
3 . The method of claim 2 , wherein the second planar surface is lower than the first planar surface.
4 . The method of claim 1 , wherein the substrate comprises a medium-voltage (MV) region, the method comprising:
forming a MV device on the MV region, wherein the MV device comprises:
a third gate structure on the substrate; and
a third epitaxial layer adjacent to the third gate structure, wherein a top surface of the third epitaxial layer comprises a second V-shape.
5 . The method of claim 4 , wherein the third epitaxial layer comprises:
a third inclined sidewall;
a fourth inclined sidewall; and
a third planar surface connecting the third inclined sidewall and the fourth inclined sidewall.
6 . The method of claim 5 , wherein the third planar surface is lower than the first planar surface.
7 . The method of claim 1 , wherein the substrate comprises the dummy region between the HV region and the LV region, the method comprising:
forming the dummy device on the dummy region, wherein the dummy device comprises:
a fourth gate structure on the substrate; and
a fourth epitaxial layer adjacent to the fourth gate structure.
8 . A semiconductor device, comprising:
a substrate having a high-voltage (HV) region, a low-voltage (LV) region, and a dummy region between the HV region and the LV region;
a HV device on the HV region, wherein the HV device comprises:
a first gate structure on the substrate; and
a first epitaxial layer adjacent to the first gate structure, wherein a top surface of the first epitaxial layer comprises a V-shape;
a LV device on the LV region, wherein the LV device comprises:
a second gate structure on the substrate; and
a second epitaxial layer adjacent to the second gate structure, wherein a top surface of the second epitaxial layer comprises a first planar surface; and
a dummy device on the dummy region, wherein the dummy device comprises:
a fourth gate structure on the substrate; and
a fourth epitaxial layer adjacent to the fourth gate structure.
9 . The semiconductor device of claim 8 , wherein the first epitaxial layer comprises:
a first inclined sidewall;
a second inclined sidewall; and
a second planar surface connecting the first inclined sidewall and the second inclined sidewall.
10 . The semiconductor device of claim 9 , wherein the second planar surface is lower than the first planar surface.
11 . The semiconductor device of claim 8 , wherein the substrate comprises a medium-voltage (MV) region, the method comprising:
a MV device on the MV region, wherein the MV device comprises:
a third gate structure on the substrate; and
a third epitaxial layer adjacent to the third gate structure, wherein a top surface of the third epitaxial layer comprises a second V-shape.
12 . The semiconductor device of claim 11 , wherein the third epitaxial layer comprises:
a third inclined sidewall;
a fourth inclined sidewall; and
a third planar surface connecting the third inclined sidewall and the fourth inclined sidewall.
13 . The semiconductor device of claim 12 , wherein the third planar surface is lower than the first planar surface.
14 . The semiconductor device of claim 8 , wherein the dummy region comprises a ring shape around the LV region.