Shallow trench isolation structures and contact patterning
A dual layer shallow isolation trench region for semiconductor structures including field effect transistors (FETs) and methods for making the same. The first layer of the shallow trench isolation region includes a dielectric material disposed between adjacent FETs. The second layer is an etch resistant material disposed on the dielectric material and has an increased etch resistance relative to the dielectric material. The etch resistant material overlays the shallow trench region to provide the dual layer shallow trench isolation region, which permits self-alignment of contacts to the source and/or drain of FETs.
1. A method of increasing a process margin for self-aligned contact formation to a field effect transistor (FET), the method comprising:
providing an array of FETs, each one of the FETs separated from an adjacent FET by a shallow trench isolation region, the FETS including a source and/or drain region;
filling the shallow trench isolation region with a first dielectric layer;
depositing a second dielectric layer onto the first dielectric layer overlaying the shallow trench isolation region to provide the shallow trench isolation region with two dielectric layers, wherein the first and second dielectric layer comprise different etch rates;
patterning the second dielectric layer to form openings overlying the shallow isolation trench region and filling the openings with an etch resistant material;
forming contact openings in the second dielectric layer to expose the source and/or drain regions, wherein the contact openings are self-aligned to the etch resistant material; and
filling the contact openings with an electrically conductive material.
2. The method of claim 1 , wherein the etch resistant material comprises a nitride material.
3. The method of claim 1 , wherein the etch resistant material comprises silicon nitride, silicon borocarbontiride, or silicon oxycarbonitride.
4. The method of claim 1 , wherein filling the electrically conductive material comprises tungsten metal.
5. The method of claim 1 , wherein the first and second dielectric layers are different materials.
6. The method of claim 1 , wherein the second dielectric material comprises an oxide.
7. The method of claim 1 , wherein the contact openings are self-aligned to the etch resistant material and a gate stack formed over channels within the FET.
8. The method of claim 1 , wherein forming the contact openings in the second dielectric layer comprises exposing the substrate to a wet etch process.
9. The method of claim 1 , wherein the FET comprises a finFET including one or more fins.
10. A method for contact patterning during fabrication of a semiconductor structure device, the method comprising:
forming a dual layer shallow trench isolation region comprising a dielectric layer and an etch resistant layer overlying the dielectric layer, wherein the etch resistant layer has an increased etch resistance relative to the dielectric layer, and wherein the shallow trench isolation region separates adjacent field effect transistors (FETs);
etching a contact opening in an oxide layer overlying a source or drain region, wherein the contact opening is self-aligning to the etch resistant layer overlying the shallow trench isolation region, and wherein the contact opening has a depth equal to a thickness of the etch resistant layer; and
filling the contact opening with an electrically conductive material.
11. The method of claim 10 , wherein the etch resistant material comprises a nitride material.
12. The method of claim 10 , wherein the etch resistant material comprises silicon nitride, silicon borocarbontiride, or silicon oxycarbonitride.
13. The method of claim 10 , wherein the electrically conductive material comprises tungsten.
14. The method of claim 10 , wherein the FETs comprise a fin-type FET (finFET) including one or more fins.
15. The method of claim 10 , wherein the oxide layer comprises a different material than the dielectric layer.