FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation
After forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, a sigma cavity is formed within the semiconductor fin on each side of the gate structure. A semiconductor buffer region composed of an un-doped stress-generating semiconductor material is epitaxially growing from faceted surfaces of the sigma cavity. Finally, a doped semiconductor region composed of a doped stress-generating semiconductor material is formed on the semiconductor buffer region to completely fill the sigma cavity. The doped semiconductor region is formed to have substantially vertical sidewalls for formation of a uniform source/drain junction profile.
1. A method of forming a semiconductor structure comprising:
forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, wherein the gate structure comprises a gate stack straddling a channel portion of the semiconductor fin and a gate spacer present on sidewalls of the gate stack;
forming a sigma cavity within the semiconductor fin on each side of the gate structure, wherein the sigma cavity comprises a horizontal tip region extending beneath the gate spacer and a V-shaped bottom region extending towards the semiconductor substrate portion;
epitaxially growing a semiconductor buffer region from faceted surfaces of the sigma cavity, wherein the semiconductor buffer region completely fills the horizontal tip region and the V-shaped bottom region of the sigma cavity, wherein an unfilled portion of the sigma cavity has substantially vertical sidewalls; and
epitaxially growing a doped semiconductor region from the semiconductor buffer region, wherein the doped semiconductor region completely fills the unfilled portion of the sigma cavity and has substantially vertical sidewalls.
2. The method of claim 1 , wherein the forming the sigma cavity comprises:
forming an initial cavity by performing an anisotropic etch to remove a portion of semiconductor fin located on each side of the gate structure, wherein the initial cavity has a sidewall vertically coincident with an outer sidewall of the gate spacer; and
forming the sigma cavity from the initial cavity by performing a wet etch, wherein the sigma cavity is formed having the faceted surfaces oriented along (111) planes.
3. The method of claim 2 , wherein anisotropic etch comprises a reactive ion etch.
4. The method of claim 2 , wherein the wet etch comprises an etchant including tetramethylammonium hydroxide (TMAH), ammonium hydroxide, or potassium hydroxide.
5. The method of claim 1 , wherein the semiconductor buffer region comprises an un-doped stress-generating semiconductor material, and the doped semiconductor region comprises a doped stress-generating semiconductor material.
6. The method of claim 5 , wherein the stress-generating semiconductor material induces a compressive stress or a tensile stress to the channel region of the semiconductor fin.
7. The method of claim 1 , wherein the semiconductor buffer region is formed by a selective epitaxial growth process, and the doped semiconductor region is formed by an in-situ doped selective epitaxial growth process.
8. The method of claim 1 , wherein a horizontal portion of the semiconductor buffer region has a thickness greater than a thickness of each vertical portion of the semiconductor buffer region.
9. The method of claim 1 , further comprising activating the dopants present in the doped semiconductor region, wherein the activating causes diffusion of the dopants from the doped semiconductor region through the semiconductor buffer region and formation of a source/drain junction between the doped semiconductor region and the channel portion of the semiconductor fin.
10. The method of claim 9 , wherein the source/drain junction has substantially vertical sidewalls.
11. A method of forming a semiconductor structure comprising:
forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, wherein the gate structure comprises a gate stack straddling a channel portion of the semiconductor fin and a gate spacer present on sidewalls of the gate stack;
forming a sigma cavity within the semiconductor fin on each side of the gate structure, wherein the sigma cavity comprises a horizontal tip region extending beneath the gate spacer and a bottom region extending towards the semiconductor substrate portion;
epitaxially growing a semiconductor buffer region from faceted surfaces of the sigma cavity, wherein the semiconductor buffer region completely fills the horizontal tip region and the bottom region of the sigma cavity, wherein an unfilled portion of the sigma cavity has substantially vertical sidewalls;
epitaxially growing a doped semiconductor region from the semiconductor buffer region, wherein the doped semiconductor region completely fills the unfilled portion of the sigma cavity and has substantially vertical sidewalls; and
forming a source/drain junction having substantially vertical sidewalls between the doped semiconductor region and the channel portion of the semiconductor fin, wherein the forming the source/drain junction comprises activating the dopants present in the doped semiconductor region, wherein the activating causes diffusion of the dopants from the doped semiconductor region through the semiconductor buffer region.