FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation

1. A method of forming a semiconductor structure comprising:

forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, wherein the gate structure comprises a gate stack straddling a channel portion of the semiconductor fin and a gate spacer present on sidewalls of the gate stack;

forming a sigma cavity within the semiconductor fin on each side of the gate structure, wherein the sigma cavity comprises a first horizontal tip region extending beneath the gate spacer and a bottom region extending towards the semiconductor substrate portion;

forming a second sigma cavity intersecting the bottom portion of the sigma cavity, wherein the second sigma cavity comprises a second horizontal tip region located beneath the first horizontal tip region, wherein the second horizontal tip region extends beneath the gate spacer and is adjacent to the channel region of the semiconductor fin;

epitaxially growing a semiconductor buffer region from faceted surfaces of the sigma cavity and the second sigma cavity, wherein the semiconductor buffer region completely fills the first and second horizontal tip regions and the bottom region of the sigma cavity, wherein an unfilled portion of the sigma cavity has substantially vertical sidewalls; and

epitaxially growing a doped semiconductor region from the semiconductor buffer region, wherein the doped semiconductor region completely fills the unfilled portion of the sigma cavity and has substantially vertical sidewalls.

2. The method of claim 1 , wherein the forming the sigma cavity comprises:

forming an initial cavity by performing an anisotropic etch to remove a portion of semiconductor fin located on each side of the gate structure, wherein the initial cavity has a sidewall vertically coincident with an outer sidewall of the gate spacer; and

forming the sigma cavity from the initial cavity by performing a wet etch, wherein the sigma cavity is formed having the faceted surfaces oriented along (111) planes.

3. The method of claim 2 , wherein anisotropic etch comprises a reactive ion etch.

4. The method of claim 2 , wherein the wet etch comprises an etchant including tetramethylammonium hydroxide (TMAH), ammonium hydroxide, or potassium hydroxide.

5. The method of claim 1 , wherein the semiconductor buffer region comprises an un-doped stress-generating semiconductor material, and the doped semiconductor region comprises a doped stress-generating semiconductor material.

6. The method of claim 5 , wherein the stress-generating semiconductor material induces a compressive stress or a tensile stress to the channel region of the semiconductor fin.

7. The method of claim 1 , wherein the semiconductor buffer region is formed by a selective epitaxial growth process, and the doped semiconductor region is formed by an in-situ doped selective epitaxial growth process.

8. The method of claim 1 , wherein a horizontal portion of the semiconductor buffer region has a thickness greater than a thickness of each vertical portion of the semiconductor buffer region.

9. The method of claim 1 , further comprising forming a third sigma cavity intersecting a bottom portion of the second sigma cavity prior to the forming the semiconductor buffer region, wherein the third sigma cavity comprises a third horizontal tip region located beneath the second horizontal tip region of the second sigma cavity, wherein the third horizontal tip region extends beneath the gate stack and is located below the channel region of the semiconductor fin, and wherein the semiconductor buffer region is epitaxially grown from faceted surfaces of the sigma cavity, the second sigma cavity and the third sigma cavity.