Vertical air gap subtractive etch back end metal

1. A method of forming a semiconductor structure comprising:

forming source/drain regions on opposite sides of a gate structure located over a channel region of a semiconductor material layer;

forming source/drain contact structures in an interlevel dielectric (ILD) layer overlying the semiconductor material layer, each of the source/drain contact structures contacting one of the source/drain regions;

recessing the ILD layer to expose an upper portion of each of the source/drain contact structures;

forming a sacrificial layer over a remaining portion of the ILD layer to laterally surround the upper portion of each of the source/drain contact structures;

forming an interconnect conductor portion over the sacrificial layer to contact at least one of the source/drain contact structures;

removing the sacrificial layer to re-expose the upper portion of each of the source/drain contact structures; and

forming an interconnect liner portion, the interconnect liner portion having a first portion present on top and sidewall surfaces of the interconnect conductor portion and a second portion enclosing an air gap located between the interconnect conductor portion and the remaining portion of the ILD layer.

2. The method of claim 1 , wherein the interconnect conductor portion comprising a contact via and a contact line extending beneath the contact via, the contact line directly contacting the at least one of the source/drain contact structures.

3. The method of claim 2 , wherein the forming the interconnect conductor portion comprises:

forming a metal layer over the sacrificial layer and the source/drain contact structures;

patterning the metal layer to form the contact via in an upper portion of the metal layer; and

patterning a remaining portion of the metal layer to form the contact line extending beneath the contact via, wherein the contact line vertically contacts the at least one of the source/drain contact structures.

4. The method of claim 3 , further comprising annealing the metal layer prior to the patterning the metal layer.

5. The method of claim 3 , wherein the metal layer comprises Cu, W, Al, Ag, Au, a multilayered stack thereof or an alloy thereof.

6. The method of claim 2 , further comprising forming a contact level dielectric layer over the interconnect liner portion and the remaining portion of the ILD layer, the contact level dielectric layer laterally surrounding the interconnect conductor portion and having a top surface coplanar with a topmost surface of the interconnect liner portion.

7. The method of claim 1 , wherein the forming the interconnect liner portion comprises:

forming an interconnect liner layer over a top surface of the remaining portion of the ILD layer and the top and sidewall surfaces of the interconnect conductor portion, wherein the interconnect liner layer pinches off a void formed by the removal of the sacrificial layer to provide the air gap; and

removing portions of the interconnect liner layer from the top surface of the remaining portion of the ILD layer to provide the interconnect liner portion.

8. The method of claim 7 , wherein the interconnect liner layer is formed by a non-conformal deposition process.

9. The method of claim 7 , wherein the interconnect liner layer comprise silicon nitride, silicon oxide or hafnium oxide.

10. The method of claim 1 , wherein the sacrificial layer comprises amorphous carbon.

11. The method of claim 10 , wherein the removing the sacrificial layer is performed by oxygen ashing.

12. The method of claim 1 , wherein the remaining portion of the ILD layer after the recessing the ILD layer has a top surface coplanar with a topmost surface of the gate structure.

13. The method of claim 1 , wherein the remaining portion of the ILD layer after the recessing the ILD layer has a top surface located above a topmost surface of the gate structure.

14. The method of claim 1 , wherein the forming the source/drain contact structures comprises:

forming source/drain contact openings extending through the ILD layer, each of the source/drain contact openings exposing at least a portion of one of the source/drain regions;

forming a contact liner layer over sidewalls and bottom surfaces of the source/drain contact openings and a top surface of the ILD layer;

forming a contact conductive material layer over the contact liner layer to completely fill the source/drain contact openings; and

removing portions of the contact conductive material layer and the contact liner layer from the top surface of the ILD layer.

15. The method of claim 14 , wherein the contact liner layer comprises Ti, Ta, Ni, Co, Pt, W, TiN, TaN, WN, WC, Ti/TiN or Ta/TaN.

16. The method of claim 14 , wherein the contact conductive material layer comprises W, Al or Cu.

17. The method of claim 1 , wherein the gate structure comprises a gate stack comprising a gate dielectric, a gate electrode and a gate cap, and a gate spacer located on sidewalls of the gate stack.

18. The method of claim 17 , further comprising forming the gate stack, wherein the forming the gate stack comprises:

forming a material stack comprising, from bottom to top, a gate dielectric layer, a gate electrode layer and a gate cap layer over the semiconductor material; and

patterning the material stack to provide the gate stack contacting the channel region of a semiconductor material layer.

19. The method of claim 18 , further comprising forming the gate spacer, wherein the forming the gate spacer comprises:

forming a conformal gate spacer material layer on exposed surfaces of the gate stack and the semiconductor material layer; and

removing horizontal portions of the gate spacer material layer.

20. The method of claim 1 , wherein the forming the source/drain regions is performed by ion implantation.