FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation
After forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, a sigma cavity is formed within the semiconductor fin on each side of the gate structure. A semiconductor buffer region composed of an un-doped stress-generating semiconductor material is epitaxially growing from faceted surfaces of the sigma cavity. Finally, a doped semiconductor region composed of a doped stress-generating semiconductor material is formed on the semiconductor buffer region to completely fill the sigma cavity. The doped semiconductor region is formed to have substantially vertical sidewalls for formation of a uniform source/drain junction profile.
1. A semiconductor structure comprising:
a gate structure located over a semiconductor fin that extends upwards from a semiconductor substrate portion, wherein the gate structure comprises a gate stack in direct contact with a top surface and opposing sidewall surfaces of a channel region of the semiconductor fin and a gate spacer present on sidewalls of the gate stack;
a sigma cavity located within the semiconductor fin on each side of the gate structure and comprising a first horizontal tip region, a second horizontal tip region located beneath the first horizontal tip region, and a bottom region extending towards the semiconductor substrate portion, and wherein the first and second horizontal tip regions extend beneath the gate spacer and are adjacent to the channel region of the semiconductor fin;
a semiconductor buffer region located on faceted surfaces of the sigma cavity, wherein the semiconductor buffer region completely fills the first horizontal tip region, the second horizontal tip region, and the bottom region of the sigma cavity; and
a doped semiconductor region having a bottom surface in direct contact with a top surface of the semiconductor buffer region that is present in the bottom region of the sigma cavity and having a sidewall surface in direct contact with a sidewall surface of the semiconductor buffer region in the first horizontal tip region of the sigma cavity, wherein the doped semiconductor region completely fills a remaining portion of the sigma cavity and has substantially vertical sidewalls.
2. The semiconductor structure of claim 1 , wherein the semiconductor buffer region comprises an un-doped stress-generating semiconductor material, and the doped semiconductor region comprises a doped stress-generating semiconductor material.
3. The semiconductor structure of claim 2 , wherein the un-doped stress-generating semiconductor material and the doped stress-generating semiconductor material induce a compressive stress to the channel region of the semiconductor fin.
4. The semiconductor structure of claim 3 , wherein each of the un-doped stress-generating semiconductor material and the doped stress-generating semiconductor material comprises SiGe.
5. The semiconductor structure of claim 2 , wherein the un-doped stress-generating semiconductor material and the doped stress-generating semiconductor material induce a tensile stress to the channel region of the semiconductor fin.
6. The semiconductor structure of claim 5 , wherein each of the un-doped stress-generating semiconductor material and the doped stress-generating semiconductor material comprises Si:C.
7. The semiconductor structure of claim 1 , wherein a horizontal portion of the semiconductor buffer region has a thickness greater than a thickness of each vertical portion of the semiconductor buffer region.
8. The semiconductor structure of claim 1 , wherein the sigma cavity further comprises a third horizontal tip region located beneath the second horizontal tip region, wherein the third horizontal tip region extends beneath the gate stack and is located below the channel region of the semiconductor fin, wherein the semiconductor buffer region completely fills the third horizontal tip region.
9. A semiconductor structure comprising:
a gate structure located over a semiconductor fin that extends upwards from a semiconductor substrate portion, wherein the gate structure comprises a gate stack straddling a channel region of the semiconductor fin and a gate spacer present on sidewalls of the gate stack;
a sigma cavity located within the semiconductor fin on each side of the gate structure and comprising a first horizontal tip region, a second horizontal tip region located beneath the first horizontal tip region and a bottom region extending towards the semiconductor substrate portion, wherein the first and second horizontal tip regions extend beneath the gate spacer and are adjacent to the channel region of the semiconductor fin;
a semiconductor buffer region located on faceted surfaces of the sigma cavity, wherein the semiconductor buffer region completely fills the first horizontal tip region, the second horizontal tip region and the bottom region of the sigma cavity; and
a doped semiconductor region located on the semiconductor buffer region, wherein the doped semiconductor region completely fills the sigma cavity and has substantially vertical sidewalls.
10. A semiconductor structure comprising:
a gate structure located over a semiconductor fin that extends upwards from a semiconductor substrate portion, wherein the gate structure comprises a gate stack straddling a channel region of the semiconductor fin and a gate spacer present on sidewalls of the gate stack;
a sigma cavity located within the semiconductor fin on each side of the gate structure and comprising a first horizontal tip region, a second horizontal tip region located beneath the first horizontal tip region, a third horizontal tip region located beneath the second horizontal tip region and a bottom region extending towards the semiconductor substrate portion, wherein the first, second and third horizontal tip regions extend beneath the gate spacer, and wherein the first and second horizontal tip regions are adjacent to the channel region of the semiconductor fin and the third horizontal tip region is located below the channel region of the semiconductor fin;
a semiconductor buffer region located on faceted surfaces of the sigma cavity, wherein the semiconductor buffer region completely fills the first horizontal tip region, the second horizontal tip region, the third horizontal tip region and the bottom region of the sigma cavity; and
a doped semiconductor region located on the semiconductor buffer region, wherein the doped semiconductor region completely fills the sigma cavity and has substantially vertical sidewalls.