IP Library Granted Patent US 10,373,909
Granted Patent B2
US 10,373,909 · App. 15/724,367 · Granted Aug 6, 2019

Selective surface modification of interconnect structures

Inventors: Raghuveer R. Patlolla (Guilderland, NY); Cornelius Brown Peethala (Albany, NY); Roger A. Quon (Rhinebeck, NY); Chih-Chao Yang (Glenmont, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L23/53238H01L21/76849H01L21/76883
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Quick Facts
Patent No.
US 10,373,909
App. No.
15/724,367
Granted
Aug 6, 2019
Kind
B2
Abstract

Semiconductor structures including copper interconnect structures and methods include selective surface modification of copper by providing a Cu x Ti y N z alloy in the surface. The methods generally include forming a titanium nitride layer on an exposed copper surface followed by annealing to form the Cu x Ti y N z , alloy in the exposed copper surface. Subsequently, the titanium layer is removed by a selective wet etching.

Claims (14)

1. A semiconductor structure comprising:

at least one copper interconnect structure filled with copper in an interlayer dielectric, the at least one copper interconnect structure comprising a Cu x Ti y N z alloy in a top surface of the copper, wherein 0<x<1, 0<y<1, and 0≤z<1, wherein the Cu x Ti y N z alloy in the top surface is free of TiN thereon.

2. The semiconductor structure of claim 1 , wherein the at least one copper interconnect structure further comprises a liner layer on surfaces between the at least one copper interconnect structure and the interlayer dielectric.

3. The semiconductor structure of claim 1 further comprising a liner layer intermediate the copper and the interlayer dielectric formed of a material comprising tantalum, titanium, tantalum nitride or titanium nitride.

4. The semiconductor structure of claim 1 , wherein the top surface of the copper is coplanar to a top surface of the interlay dielectric.

5. The semiconductor structure of claim 1 , wherein the copper includes an alloying element comprising C, N, O, or Cl.

6. The semiconductor structure of claim 1 , wherein the copper further comprises an amount of an alloying element is in the range of about 0.001 weight percent (wt. %) to about 10 wt % of the copper.

7. The semiconductor structure of claim 1 , wherein the interlayer dielectric comprises silicon dioxide, silicon nitride, or a doped glass layer, such as phosphorus silicate glass, or boron silicate glass.

8. The semiconductor structure of claim 3 , wherein the liner layer comprises tantalum, tantalum, nitride, cobalt, ruthenium, titanium nitride, or combinations thereof.

9. The semiconductor structure of claim 2 , further comprising a seed layer on the liner layer, the seed layer comprising one or more metals.

10. The semiconductor structure of claim 9 , wherein the seed layer comprising the one or more metals is from 1 atomic percent to 10 atomic percent.

11. The semiconductor structure of claim 9 , wherein the seed layer comprises copper or copper manganese.

12. The semiconductor structure of claim 9 , wherein the seed layer comprising the one or more metals is from 1 atomic percent to 7 atomic percent.

13. The semiconductor structure of claim 5 , wherein the alloying element is from 0.001 weight percent to 10 weight percent.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052644/0868 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2017
From: PATLOLLA, RAGHUVEER R.; PEETHALA, CORNELIUS BROWN; QUON, ROGER A.; YANG, CHIH-CHAO
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 043777/0351 →
Continuity (2)
Division 15268787 · Sep 19, 2016
Related Publication 20180082955A1 · Mar 22, 2018