Vertical FET with different channel orientations for NFET and PFET
A technique relates to forming a semiconductor device. A first substrate is provided adjacent to a second substrate. The first substrate has a first surface orientation, and the second substrate has a second surface orientation different from the first surface orientation. An n-type field effect transistor (NFET) device is formed with the first substrate. The NFET device includes a first source, a first drain, and one or more first fins. The first source and the first drain have a vertical relationship with respect to the one or more first fins. A p-type field effect transistor (PFET) device is formed with the second substrate. The PFET device includes a second source, a second drain, and one or more second fins. The second source and the second drain have a vertical relationship with respect to the one or more second fins.
1. A method of forming a semiconductor device, the method comprising:
providing a first silicon wafer bonded to a second silicon wafer, the first silicon wafer having a first surface orientation, the second silicon wafer having a second surface orientation different from the first surface orientation;
forming an n-type field effect transistor (NFET) device with the first silicon wafer, the NFET device including a first source, a first drain, and one or more first fins, wherein the first source and the first drain have a vertical relationship with respect to the one or more first fins; and
forming a p-type field effect transistor (PFET) device with the second silicon wafer, the PFET device including a second source, a second drain, and one or more second fins, wherein the second source and the second drain have a vertical relationship with respect to the one or more second fins.
2. The method of claim 1 , wherein the first source, the first drain, and the one or more first fins have the first surface orientation as the first silicon wafer.
3. The method of claim 1 , wherein the second source, the second drain, and the one or more second fins have the second surface orientation as the second silicon wafer.
4. The method of claim 1 , wherein the first one or more fins have a first channel transport direction and the second one or more fins have a second channel transport direction, the first channel transport direction being different from the second channel transport direction.
5. The method of claim 4 , wherein the first channel transport direction is defined to be suited for mobility of electrons and the second channel transport direction is defined to be suited for mobility of holes.
6. The method of claim 4 , wherein the first channel transport direction is different from the first surface orientation.
7. The method of claim 4 , wherein the second channel transport direction is different from the second surface orientation.
8. The method of claim 4 , wherein the first channel transport direction is <100> and the second channel transport direction is <110>.
9. The method of claim 1 , wherein the first surface orientation is <001>.
10. The method of claim 1 , wherein the second surface orientation is <1-10>.
11. A semiconductor device comprising:
a first silicon wafer bonded to a second silicon wafer, the first silicon wafer having a first surface orientation, the second silicon wafer having a second surface orientation different from the first surface orientation;
an n-type field effect transistor (NFET) device formed with the first silicon wafer, the NFET device including a first source, a first drain, and one or more first fins, wherein the first source and the first drain have a vertical relationship with respect to the one or more first fins; and
a p-type field effect transistor (PFET) device formed with the second silicon wafer, the PFET device including a second source, a second drain, and one or more second fins, wherein the second source and the second drain have a vertical relationship with respect to the one or more second fins.
12. The semiconductor device of claim 11 , wherein the first source, the first drain, and the one or more first fins have the first surface orientation as the first silicon wafer.
13. The semiconductor device of claim 11 , wherein the second source, the second drain, and the one or more second fins have the second surface orientation as the second silicon wafer.
14. The semiconductor device of claim 11 , wherein the first one or more fins have a first channel transport direction and the second one or more fins have a second channel transport direction, the first channel transport direction being different from the second channel transport direction.
15. The semiconductor device of claim 14 , wherein the first channel transport direction is defined to be suited for mobility of electrons and the second channel transport direction is defined to be suited for mobility of holes.
16. The semiconductor device of claim 14 , wherein the first channel transport direction is different from the first surface orientation.
17. The semiconductor device of claim 14 , wherein the second channel transport direction is different from the second surface orientation.
18. The semiconductor device of claim 14 , wherein the first channel transport direction is <100> and the second channel transport direction is <110>.
19. The semiconductor device of claim 11 , wherein the first surface orientation is <001> and the second surface orientation is <1-10>.